IRMCK099M
List of Figures
FIGURE 1. TYPICAL APPLICATION BLOCK DIAGRAM USING IRMCK099 ...................................................................................5
FIGURE 2. PINOUT OF IRMCK099 .............................................................................................................................................6
FIGURE 3. IRMCK099 BLOCK DIAGRAM....................................................................................................................................8
FIGURE 4. IRMCK099 LEG SHUNT CONNECTION DIAGRAM.....................................................................................................9
FIGURE 5. VOLTAGE DROOP AND S/H HOLD TIME ....................................................................................................................16
FIGURE 6. OP AMP OUTPUT CAPACITOR ...................................................................................................................................17
FIGURE 7. SYNC TIMING...........................................................................................................................................................18
FIGURE 8. FAULT TIMING...........................................................................................................................................................19
FIGURE 9. ITRIP TIMING ...........................................................................................................................................................19
FIGURE 10. I2C TIMING .............................................................................................................................................................20
FIGURE 11. UART TIMING.........................................................................................................................................................21
FIGURE 12. CAPTURE TIMING ................................................................................................................................................22
FIGURE 13. JTAG TIMING .........................................................................................................................................................23
FIGURE 14. DIGITAL I/O STRUCTURE .......................................................................................................................................24
FIGURE 15. ANALOG I/O STRUCTURE ......................................................................................................................................24
FIGURE 16 ANALOG ANALOG INPUT STRUCTURE FOR AIN0/STBY.......................................................................................24
FIGURE 17. VSS PIN I/O STRUCTURE.......................................................................................................................................25
FIGURE 18. VDDCAP PIN I/O STRUCTURE..............................................................................................................................25
FIGURE 19. VDD1 PIN I/O STRUCTURE....................................................................................................................................25
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© 2014International Rectifier
December 18, 2014