5秒后页面跳转
IMP16C552-CJ68 PDF预览

IMP16C552-CJ68

更新时间: 2024-02-17 09:09:56
品牌 Logo 应用领域
IMP 先进先出芯片
页数 文件大小 规格书
34页 752K
描述
Dual Universal Asynchronous Receiver/Transmitter (UART) with 16-BYTE FIFO & Parallel Printer Port

IMP16C552-CJ68 数据手册

 浏览型号IMP16C552-CJ68的Datasheet PDF文件第2页浏览型号IMP16C552-CJ68的Datasheet PDF文件第3页浏览型号IMP16C552-CJ68的Datasheet PDF文件第4页浏览型号IMP16C552-CJ68的Datasheet PDF文件第6页浏览型号IMP16C552-CJ68的Datasheet PDF文件第7页浏览型号IMP16C552-CJ68的Datasheet PDF文件第8页 
IMP16C552  
Mnemonic  
RESET  
Pin  
type  
Pin#  
39  
description  
IN  
Master reset: When this input is low it clears all the register(except the  
Receiver Buffer, Transfer Holding and Divisor Latches) and the control  
logic of the both channels and parallel port the states of various output  
signals are affected by an active RESET input (refer to table 1) .this  
input is buffered with a TTL-compatible schmitt trigger with 0.5v  
hysteresis.  
SIN0 STS1 IN  
41.62  
28.13  
Serial inputs :Serial data input from the communication link such as  
peripheral device , MODE or data set to the associated serial channel  
DSR0*,  
DSR1*  
IN  
Clear To Send: When low this pin indicates that the MODEM or data  
set is ready to exchange data The CTS0(1)*.signal is a MODEM status  
input whose conditions can be tested by the CPU reading bit4(CTS)of  
the MODEM Status Register Bit4 is the complement of the CTS0(1)  
signal Bit 0 (DCTS )of the MODEM status register indicates whether the  
CTS(1)* input has changed state since the previous reading of the  
modem status register CTS0(1)* has no the Transmitter  
Note: whenever the CTS bit of the MODEM status register changes  
state an interrupt is generated if the MODEM status interrupt is enabled  
DSR0*  
DSR1*  
IN  
31.5  
29.8  
30.6  
Data Set Ready :When low this pin indicates that modem or data set is  
ready to establish the communication link with the UART the DSR0(1)  
signal is a MODEM status input whose condition can be tested by the  
CPU reading bit 5 (DSR)of the MODEM status register bit 5 is the  
complement of the DSR0(1)* signal. bit 1 (DDSR) of the MODEM Status  
Register Indicates whether the DSR0(1)* input has changed state since  
the previous reading of the MODEM Status Register DSR0(1)* has no  
the transmitter  
Note: Whenever the DSR bit of the MODEM Status Register changes  
state, an interrupt is generated if the MODEM status interrupt is enable  
RLSD0*  
RISD1*  
IN  
Receiver Line Signal Detect: When low ,this pin indicates that the data  
canter has been detected by the MODEM or data set The RLSD0(1)*  
signal is a MODEM status input whose condition can be tested by the  
CPU reading bit 7(RLSD)of the MODEM Status Register Bit 7 is the  
complement of the RLSD0(1)* signal. Bit 3 (DRLSD) of the MODEM  
Status Register indicates whether the RLSD0(1)* input has changed  
state since the previous reading of the MODEM Status Register  
RLSD0(1)* has no effect on the receive  
Note: whenever the RLSD bit of the MODE status register changes state  
on interrupt is generated if the MODEM status interrupt is enable  
RI0* RI1*  
IN  
Ring indicator : when low this pin indicates that a telephone ringing  
signal has been received by the MODEM or data set The RI0(1)* signal  
is a MODEM status input whose condition can be tested by the CPU  
reading bit 6 (RI) of the MODEM Status Register Bit 6 is the  
complement of the RI0(1) signal Bit2 (TERI) of MODEM Status  
Register indicates whether the RI0(1) input signal has changed from a  
low to a high state since the previous reading of the MODEM Status  
Register.  
Note: whenever the RI bit of the MODEM Status Register changes from  
a low to a high state an interrupt is generated if the MODEM status  
interrupt is enabled  
23.40.64  
VCC  
VSS  
IN  
+5V supply  
Ground  
2.7.27  
43.54  
5
408-432-9100/ www.impweb.com  
© 2002 IMP, Inc.  

与IMP16C552-CJ68相关器件

型号 品牌 获取价格 描述 数据表
IMP16C552-IJ68 IMP

获取价格

Dual Universal Asynchronous Receiver/Transmitter (UART) with 16-BYTE FIFO & Parallel Print
IMP16C554 IMP

获取价格

Quad Universal Asynchronous Receiver/Transmitter (UART) with FIFOs
IMP16C554-CJ68 IMP

获取价格

Quad Universal Asynchronous Receiver/Transmitter (UART) with FIFOs
IMP16C554-LJ68 IMP

获取价格

Quad Universal Asynchronous Receiver/Transmitter (UART) with FIFOs
IMP1810 IMP

获取价格

Low Power, 5V, P Reset
IMP1810 A1PROS

获取价格

Low Power,, 5V - Ressett- Acttiive LOW,, Open--Draiin Outtputt
IMP1811 A1PROS

获取价格

Low Power,, 5V - Ressett- Acttiive LOW,, Open--Draiin Outtputt
IMP1811 IMP

获取价格

Low Power, 5V, P Reset
IMP1812 IMP

获取价格

Low Power, 5V, P Reset
IMP1812 A1PROS

获取价格

Low Power,, 5V - Ressett- Acttiive LOW,, Open--Draiin Outtputt