IDT821068 OCTAL PROGRAMMABLE PCM CODEC
INDUSTRIAL TEMPERATURE RANGE
GCI MODE
Compressed GCI Structure
In GCI compressed mode, the Data Upstream Interface logic con-
In GCI mode, the GCI interface provides communication of both
control and voice data between the GCI bus and SLIC over a pair of trols the transmission of data onto the GCI bus. One GCI frame con-
pins (DD and DU). The IDT821068 follows the GCI standard where sists of 8 GCI time slots, and one GCI time slot consists of four 8-bit
voice and control data for eight channels are combined into one serial bytes as described below:
bit stream: Data Upstream is sent out of the DU pin and Data
- Two voice data bytes from the A-law or m-law compressor for two
Downstream is received on the DD pin. The data transmission is different channels. For easy description, we name the two channels as
controlled by the Data Clock (DCL) and Frame Synchronization (FSC) channel A and channel B. The compressed voice data bytes for chan-
signals. The Frame Sync (FSC) pulse identifies the beginning of the nel A and B are 8-bit wide;
Transmit and Receive frames and all GCI time slots refer to it. The
- One monitor channel byte, which is used for reading control data
DCL signal can be 2.048MHz or 4.096 MHz, decided by DOUBLE from the device for channel A and B;
pin. The IDT821068 adjusts internal timing to accommodate signal
- One C/I channel byte, which contains a 6 bit width C/I channel sub-
(2.048 MHz) or double (4.096 MHz) clock rate. A complete GCI frame byte together with an MX bit and an MR bit. All real time signaling in-
is sent upstream on DU pin and received downstream on DD pin formation is carried on the C/I channel sub-byte. The MX (Monitor
every 125 ms.
In GCI mode, IDT821068 supports compressed and linear voice functions for channel A and B. Both MX and MR are active low.
data format. To make the selection, users should set the MPI and CS The data structure of the Data Downstream is as same as that of
pin to correct level as shown in the following table, and at the same Upstream. The Data Downstream Interface logic controls the reception
Transmit) bit and MR (Monitor Receive) bits are used for handshaking
time, set the DMS bit in Global Command accordingly.
of data bytes from the GCI bus. The two compressed voice channel
data bytes of the GCI time slot are transferred to the A-law or m-law ex-
pansion logic circuit. The expanded data is passed to the receive path
of the signal processor. The monitor channel and C/I channel bytes are
transferred to the GCI control logic for processing.
Voice Data Format
MPI
1
CS
0
Compressed GCI
Linear GCI
1
1
Figure 4 shows the overall compressed GCI frame structure.
In compressed operation, four time slots are required to access the
eight channels of IDT821068. The GCI time slot assignment is
determined by the TS pin as shown in Table 1.
125
m
s
FSC
DCL
TS0
TS1
TS1
TS2
TS2
TS3
TS4
TS4
TS5
TS5
TS6
TS6
TS7
TS7
DD
DU
Detail
TS0
TS3
Detail
M M
Voice Channel A
Voice Channel A
Voice Channel B
Voice Channel B
Monitor Channel C/I Channel
Monitor Channel C/I Channel
DD
R
X
M M
DU
R
X
Figure 4. Compressed GCI Frame Structure
Table 1 - Time Slot Selection for compressed GCI
IDT821068
TS = 0
TS = 1
Channels
Timeslot
Timeslot0
Timeslot0
Timeslot1
Timeslot1
Timeslot2
Timeslot2
Timeslot3
Timeslot3
Voice Channel
Timeslot
Timeslot4
Timeslot4
Timeslot5
Timeslot5
Timeslot6
Timeslot6
Timeslot7
Timeslot7
Voice Channel
1
2
3
4
5
6
7
8
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
7