IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ThecontentsoftheoffsetregisterscanbereadonthedataoutputlinesQ0-
IfsynchronousPAE/PAFconfigurationisselected,thePAEisassertedand
Q11 whentheLDpinissetLOWandRENissetLOW.Datacanthenberead updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is
onthenextLOW-to-HIGHtransitionofRCLK. ThefirsttransitionofRCLKwill assertedandupdatedontherisingedgeofWCLKonlyandnotRCLK.Fordetail
presenttheemptyoffsetvaluetothedataoutputlines.ThenexttransitionofRCLK timingdiagrams,seeFigure22forsynchronousPAEtimingandFigure23for
willpresentthefulloffsetvalue.OffsetregistercontentcanbereadoutintheIDT synchronousPAFtiming.
Standard mode only. It cannot be read in the FWFT mode.
REGISTER-BUFFERED FLAG OUTPUT SELECTION
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG TIM-
ING SELECTION
The IDT72V205/72V215/72V225/72V235/72V245 can be configured
duringthe"ConfigurationatReset"cycledescribedinTable4withsingle,double
The IDT72V205/72V215/72V225/72V235/72V245 can be configured ortripleregister-bufferedflagoutputsignals.Thevariouscombinationsavail-
during the "Configuration at Reset" cycle described in Table 3 with either able are described in Table 4 and Table 5. In general, going from single to
asynchronous orsynchronous timingforPAEand PAF flags.
doubleortriplebufferedflagoutputsremovesthepossibilityofmetastableflag
Ifasynchronous PAE/PAF configurationis selected(as perTable3),the indicationsonboundarystates(i.e,emptyorfullconditions).Thetrade-offisthe
PAEisassertedLOWontheLOW-to-HIGHtransitionofRCLK.PAEisresetto addition of clock cycle delays for the respective flag to be asserted. Not all
HIGHontheLOW-to-HIGHtransitionofWCLK.Similarly,thePAFisasserted combinationsof register-bufferedflagoutputsaresupported.Register-buffered
LOWontheLOW-to-HIGHtransitionofWCLKandPAFisresettoHIGHonthe outputsapplytotheEmptyFlagandFullFlagonly. Partialflagsarenoteffected.
LOW-to-HIGHtransitionofRCLK.Fordetailtimingdiagrams,seeFigure13for Table 4andTable 5summarize the options available.
asynchronous PAEtimingandFigure14forasynchronous PAFtiming.
TABLE 1 STATUS FLAGS FOR IDT STANDARD MODE
Number of Words in FIFO
IDT72V205
IDT72V215
IDT72V225
IDT72V235
IDT72V245
FF PAF HF PAE EF
0
0
1 to n(1)
0
0
1 to n(1)
0
1 to n(1)
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to n(1)
1 to n(1)
(n + 1) to 128
129 to (256-(m+1))(2)
(256-m)to255
(n + 1) to 256
257 to (512-(m+1))(2)
(512-m)to511
512
(n + 1) to 512
513 to (1,024-(m+1))(2)
(1,024-m)to1,023
1,024
(n + 1) to 1,024
1,025 to (2,048-(m+1))(2)
(2,048-m)to2,047
2,048
(n + 1) to 2,048
2,049 to (4,096-(m+1))(2)
(4,096-m)to4,095
4,096
H
H
H
H
256
L
NOTES:
1. n = Empty Offset (Default Values : IDT72V205 n=31, IDT72V215 n = 63, IDT72V225/72V235/72V245 n = 127)
2. m = Full Offset (Default Values : IDT72V205 m=31, IDT72V215 m = 63, IDT72V225/72V235/72V245 m = 127)
TABLE 2 STATUS FLAGS FOR FWFT MODE
Number of Words in FIFO
IDT72V205
IDT72V215
IDT72V225
IDT72V235
IDT72V245
IR PAF HF PAE OR
0
0
1 to (n + 1)(1)
(n + 2) to 257
258 to (513-(m+1))(2)
(513-m) to 512
513
0
0
0
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
L
L
H
L
L
L
L
L
1 to (n + 1)(1)
1 to (n + 1)(1)
(n + 2) to 513
514 to (1,025-(m+1))(2)
(1,025-m) to 1,024
1,025
1 to (n + 1)(1)
1 to (n + 1)(1)
(n + 2) to 129
130 to (257-(m+1))(2)
(257-m) to 256
(n + 2) to 1,025
1,026 to (2,049-(m+1))(2)
(2,049-m) to 2,048
2,049
(n + 2) to 2,049
2,050 to (4,097-(m+1))(2)
(4,097-m) to 4,096
4,097
H
H
H
H
257
L
NOTES:
1. n = Empty Offset (Default Values : IDT72V205 n = 31, IDT72V215 n = 63, IDT72V225/72V235/72V245 n = 127)
2. m = Full Offset (Default Values : IDT72V205 m = 31, IDT72V215 m = 63, IDT72V225/72V235/72V245 m = 127)
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