IDT23S08E-2PG8

更新时间： 2024-01-13 09:30:35

品牌	Logo	应用领域
艾迪悌 - IDT		时钟驱动光电二极管时钟驱动器
页数	文件大小	规格书
10页	72K
描述
Clock Driver, PDSO16

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数据手册

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IDT23S08E-2PG8 数据手册

IDT23S08E

3.3VZERODELAYCLOCKMULTIPLIER

COMMERCIALANDINDUSTRIALTEMPERATURERANGES

3.3V ZERO DELAY CLOCK

MULTIPLIER, SPREAD

IDT23S08E

SPECTRUM COMPATIBLE

FEATURES:

DESCRIPTION:

• Phase-Lock Loop Clock Distribution for Applications ranging

from 10MHz to 200MHz operating frequency

• Distributes one clock input to two banks of four outputs

• Separate output enable for each output bank

• External feedback (FBK) pin is used to synchronize the outputs

to the clock input

TheIDT23S08Eis ahigh-speedphase-lockloop(PLL)clockmultiplier.It

isdesignedtoaddresshigh-speedclockdistributionandmultiplicationapplica-

tions.Thezerodelayisachievedbyaligningthephasebetweentheincoming

clockandtheoutputclock,operablewithintherangeof10to200MHz.

TheIDT23S08Ehastwobanksoffouroutputseachthatarecontrolledvia

twoselectaddresses.Byproperselectionofinputaddresses,bothbankscan

beputintri-statemode.Intestmode,thePLListurnedoff,andtheinputclock

directlydrives theoutputs forsystemtestingpurposes.Intheabsenceofan

inputclock,theIDT23S08Eenterspowerdown.Inthismode,thedevicewill

• Output Skew <200 ps

• Low jitter <200 ps cycle-to-cycle

• 1x, 2x, 4x output options (see table):

– IDT23S08E-1 1x

– IDT23S08E-2 1x, 2x

– IDT23S08E-3 2x, 4x

drawlessthan12µAforCommercialTemperaturerangeandlessthan25µA

forIndustrialtemperaturerange,andtheoutputsaretri-stated.

The IDT23S08E is available in six unique configurations for both pre-

scaling and multiplication of the Input REF Clock. (See available options

table.)

ThePLLisclosedexternallytoprovidemoreflexibilitybyallowingtheuser

tocontrolthedelaybetweentheinputclockandtheoutputs.

The IDT23S08E is characterized for both Industrial and Commercial

operation.

– IDT23S08E-4 2x

– IDT23S08E-1H, -2H, and -5H for High Drive

• No external RC network required

• Operates at 3.3V VDD

• Spread spectrum compatible

• Available in SOIC and TSSOP packages

FUNCTIONALBLOCKDIAGRAM

(-3, -4)

FBK

REF

CLKA1

PLL

(-5)

CLKA2

CLKA3

CLKA4

Control

Logic

(-2, -3)

CLKB1

CLKB2

CLKB3

CLKB4

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

MARCH 2006

2006 Integrated Device Technology, Inc.

DSC 6499/7

12 3 4 5 6 7...10

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