9DB233AFLF

更新时间： 2024-01-24 09:01:23

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
14页	197K
描述
Two Output Differential Buffer for PCIe Gen3

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9DB233AFLF 数据手册

DATASHEET

Two Output Differential Buffer for PCIe Gen3

Features/Benefits:

9DB233

Recommended Application:

•

OE# pins/Suitable for Express Card applications

2 output PCIe Gen3 zero-delay/fanout buffer

PLL or bypass mode/PLL can dejitter incoming clock

Selectable PLL bandwidth/minimizes jitter peaking in

downstream PLL's

General Description:

The 9DB233 zero-delay buffer supports PCIe Gen3

requirements, while being backwards compatible to PCIe

Gen2 and Gen1. The 9DB233 is driven by a differential SRC

output pair from an IDT 932S421 or 932SQ420 or equivalent

main clock generator. It attenuates jitter on the input clock

and has a selectable PLL bandwidth to maximize

performance in systems with or without Spread-Spectrum

clocking. An SMBus interface allows control of the PLL

bandwidth and bypass options, while 2 clock request (OE#)

pins make the 9DB233 suitable for Express Card

applications.

•

Spread Spectrum Compatible/tracks spreading input

clock for low EMI

SMBus Interface/unused outputs can be disabled

Output Features:

•

2 - 0.7V current mode differential output pairs (HCSL)

Key Specifications:

•

Cycle-to-cycle jitter < 50 ps

Output-to-output skew < 50 ps

PCIe Gen3 phase jitter < 1.0ps RMS

Block Diagram

OE0#

OE1#

DIF_0

DIF_1

SRC_IN

SPREAD

COMPATIBLE

PLL

SRC_IN#

PLL_BW

SMBDAT

SMBCLK

CONTROL

LOGIC

IREF

IDT^®Two Output Differential Buffer for PCIe Gen3

1667C—04/20/11

12 3 4 5 6 7...14

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