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HY5V56DFP-H PDF预览

HY5V56DFP-H

更新时间： 2024-02-08 02:18:39
品牌 Logo 应用领域
海力士 - HYNIX 时钟动态存储器内存集成电路
页数 文件大小 规格书
14页 253K
描述
Synchronous DRAM, 16MX16, 5.4ns, CMOS, PBGA54, 8 X 13.50 MM, 0.80 MM PITCH, LEAD FREE, FBGA-54

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HY5V56DFP-H 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：TFBGA, BGA54,9X9,32
针数：54Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.24
风险等级：5.84访问模式：FOUR BANK PAGE BURST
最长访问时间：5.4 ns其他特性：AUTO/SELF REFRESH
最大时钟频率 (fCLK)：133 MHzI/O 类型：COMMON
交错的突发长度：1,2,4,8JESD-30 代码：R-PBGA-B54
JESD-609代码：e1长度：13.5 mm
内存密度：268435456 bit内存集成电路类型：SYNCHRONOUS DRAM
内存宽度：16功能数量：1
端口数量：1端子数量：54
字数：16777216 words字数代码：16000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：16MX16
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TFBGA封装等效代码：BGA54,9X9,32
封装形状：RECTANGULAR封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified刷新周期：8192
座面最大高度：1.1 mm自我刷新：YES
连续突发长度：1,2,4,8,FP最大待机电流：0.001 A
子类别：DRAMs最大压摆率：0.22 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：20宽度：8 mm
Base Number Matches：1

HY5V56DFP-H 数据手册

 浏览型号HY5V56DFP-H的Datasheet PDF文件第1页浏览型号HY5V56DFP-H的Datasheet PDF文件第3页浏览型号HY5V56DFP-H的Datasheet PDF文件第4页浏览型号HY5V56DFP-H的Datasheet PDF文件第5页浏览型号HY5V56DFP-H的Datasheet PDF文件第6页浏览型号HY5V56DFP-H的Datasheet PDF文件第7页 
HY5V56D(L/S)FP Series  
4 Banks x 4M x 16bits Synchronous DRAM  
DESCRIPTION  
The HY5V56D(L/S)FP is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the Mobile applications which  
require low power consumption and industrial temperature range. HY5V56D(L/S)FP is organized as 4banks of  
4,194,304x16  
HY5V56D(L/S)FP is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-  
puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very  
high bandwidth. All input and output voltage levels are compatible with LVTTL.  
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write  
cycles initiated by a single control command (Burst length of 1,2,4,8, or full page), and the burst count  
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate  
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined  
design is not restricted by a `2N` rule.)  
FEATURES  
•
•
•
•
Single 3.3±0.3V power supply  
•
•
•
Auto refresh and self refresh  
All device balls are compatible with LVTTL interface  
54Ball FBGA (13.5mm x 8.0mm)  
8192 refresh cycles / 64ms  
Programmable Burst Length and Burst Type  
- 1, 2, 4, 8 or Full page for Sequential Burst  
- 1, 2, 4 or 8 for Interleave Burst  
Programmable CAS Latency ; 2, 3 Clocks  
All inputs and outputs referenced to positive edge of  
system clock  
•
•
Data mask function by UDQM or LDQM  
Internal four banks operation  
•
ORDERING INFORMATION  
Part No.  
Clock Frequency  
Power  
Organization  
Interface  
Package  
HY5V56DFP-H  
HY5V56DFP-8  
133MHz  
125MHz  
100MHz  
100MHz  
133MHz  
125MHz  
100MHz  
100MHz  
Normal  
HY5V56DFP-P  
54ball FBGA  
/
HY5V56DFP-S  
4Banks x 4Mbits x16  
LVTTL  
HY5V56D(L/S)FP-H  
HY5V56D(L/S)FP-8  
HY5V56D(L/S)FP-P  
HY5V56D(L/S)FP-S  
Lead free  
Low  
power  
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for  
use of circuits described. No patent licenses are implied.  
Rev. 0.1 / Jan. 2005  
2
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与HY5V56DFP-H相关器件

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HY5V56DFP-P HYNIX Synchronous DRAM, 16MX16, 6ns, CMOS, PBGA54, 8 X 13.50 MM, 0.80 MM PITCH, LEAD FREE, FBGA-

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HY5V56DLF-P HYNIX Synchronous DRAM, 16MX16, 6ns, CMOS, PBGA54, 13.50 X 8 MM, 0.80 MM PITCH, FBGA-54

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HY5V56DLFP-8 HYNIX Synchronous DRAM, 16MX16, 6ns, CMOS, PBGA54, 8 X 13.50 MM, 0.80 MM PITCH, LEAD FREE, FBGA-

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HY5V56DLFP-H HYNIX Synchronous DRAM, 16MX16, 5.4ns, CMOS, PBGA54, 8 X 13.50 MM, 0.80 MM PITCH, LEAD FREE, FBG

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HY5V56DLFP-S HYNIX Synchronous DRAM, 16MX16, 6ns, CMOS, PBGA54, 8 X 13.50 MM, 0.80 MM PITCH, LEAD FREE, FBGA-

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HY5V56DSF-P HYNIX Synchronous DRAM, 16MX16, 6ns, CMOS, PBGA54, 13.50 X 8 MM, 0.80 MM PITCH, FBGA-54

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