Datasheet > HPFC-5166A

HPFC-5166A

更新时间： 2024-02-21 13:16:03

品牌	Logo	应用领域
其他 - ETC		外围集成电路控制器
页数	文件大小	规格书
4页	164K
描述
Controller Miscellaneous - Datasheet Reference

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HPFC-5166A 技术参数

生命周期：	Obsolete	包装说明：	BGA,
Reach Compliance Code：	unknown	ECCN代码：	4A994.J
HTS代码：	8542.39.00.01	风险等级：	5.64
JESD-30 代码：	S-PBGA-B388	端子数量：	388
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装形状：	SQUARE	封装形式：	GRID ARRAY
认证状态：	Not Qualified	表面贴装：	YES
技术：	CMOS	端子形式：	BALL
端子位置：	BOTTOM	uPs/uCs/外围集成电路类型：	MICROPROCESSOR CIRCUIT
Base Number Matches：	1

HPFC-5166A 数据手册

Tachyon TS

66 MHz PCI to Fibre Channel

Controller

Technical Data

HPFC-5166A

Tachyon TS focuses on mass

storage applications for any

topology that require Class 3 and

Class 2 (via software), and SCSI

upper layer protocol handling.

Coupled with a high performance

66 MHz, 32/64-bit PCI bus inter-

face, Tachyon TS provides a cost-

Features

• Supports All Fibre Channel

Topologies; Arbitrated Loop

(FC-AL) and N_Port Fabric

Attachment

• Supports Class 3 and Class 2

(via Software)

• 66 MHz, 32/64-Bit PCI

Interface

effective, high-performance mass

storage solution.

• 1 Gigabit/Second Fibre

Channel Rate

• Full Duplex Support with

Parallel Inbound and

Outbound Processing

• Complete Hardware Handling

of Entire SCSI I/O via FCP

On-Chip Assists

• Full Initiator and Target

Mode Functionality

TACHYON Architecture

Tachyon TS continues with the

TACHYON architecture, a

complete hardware-based state

FC-AL Features

In addition to the high-perfor-

mance architecture, Tachyon TS

machine design. This architecture builds on the Tachyon TL with

does not require an additional on-

board microprocessor and there-

fore avoids reduced performance

issues relating to processor cycles

per second and access time to

firmware. Rather, the TACHYON

architecture is designed to be a

Public Loop, multiple I/Os in the

same loop arbitration cycle, Loop

Map, Loop Broadcast, and Loop

Directed Reset while offering 66

MHz PCI connectivity. These

features allow the designer to

achieve higher performance in an

Applications

• Motherboard Integration

• Host-Based Adapters

• Storage Subsystems

single chip Fibre Channel solution. arbitrated loop topology.

Tachyon TS provides the highest

levels of concurrency via

numerous independent functional

blocks providing parallel

processing of data, control, and

commands. In addition, these

blocks process at hardware speeds strated performance of the

versus firmware speeds, and

automate the entire SCSI I/O in

hardware. The result is minimized configuration dependent limita-

latency and I/O overhead, coupled

with the highest levels of parallel-

ism to provide maximum I/O rates

and bandwidth.

Physical Layer

• I O Designs

The physical layer interface is the

popular 10-bit wide specification

that allows interfacing to a low-

cost serializer/deserializer

Description

The HPFC-5166A, Tachyon TS, is

a second-generation controller that

leverages extensive experience in

Fibre Channel, established with

the original TACHYON controller.

Tachyon TS carries forward the

assurance of interoperability and

true Fibre Channel performance.

(SerDes) IC. The stable, demon-

-14

SerDes with BER>10 avoids

the random occurrences and

tions introduced by current

integrated implementations that

exhibit degraded signal integrity

and jitter tolerance.

12 3 4

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