Datasheet > HPFC-5750B

HPFC-5750B

更新时间： 2023-01-03 00:47:16

品牌	Logo	应用领域
安捷伦 - AGILENT		/
页数	文件大小	规格书
3页	113K
描述
Micro Peripheral IC

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HPFC-5750B 数据手册

Agilent HPFC-5700/HPFC-5750

Tachyon DX4+ Dual-Channel

4-Gb Fibre Channel Controller

Product Overview

Features

• Single chip dual port Fibre

Channel for the lowest FC solution

costs

Product Description

PCI Compliance

• 4, 2 and 1 Gb Fibre Channel

• Specification, Rev 2.2

The Tachyon DX4+ (HPFC-57xx

product series) is a high-

performance, dual port, 4/2/1

Gb/s, Fibre Channel to PCI/

PCI-X native interface

operation support via internal

• PCI Local Bus PCI-X Addendum,

transceivers

Rev 1.0A

• MNID support for Loop and point-

• MSI (Message Signaled

to-point modes

Interrupt) support

• Supports fabric, point-to-point

(N_Port) and loop (Public and

Private) topologies

controller. DX4+ is the

• PCI/PCI-X hot plug compatible

• FC-AL-2 ANSI Standard

• Hardware Design Guide for

Microsoft Windows NT Server,

Version 2.0

industry leader in 4Gb/s and is

Agilent’s sixth generation Fibre

Channel Protocol IC. The

DX4+ can be used in a variety

of high performance I/O

• Fully assisted Class 2 and Class 3

FCP with simultaneous initiator

and target functionality

applications; host bus adapters

and embedded sub-systems.

• Supports ACK_0 and ACK_1

• Compatible with ACPI/Power

models in hardware

Management Specification

• Non-zero login BB_Credit support

The DX4+ interfaces directly to

an industry standard PCI/PCI-

X bus and includes an internal

SERDES capable of supporting

4/2/1 Gb/s data rates. It

• Dual function industry standard

66 MHz PCI or 66/100/133 MHz

PCI-X backplane interface with

32/64 bit support

• Concurrent channel operation at

full link rate

• 4K on-chip boot RAM

• Virtual N_Port ID

• Eight full-frame inbound buffers

and four full-frame outbound

buffers per channel

• 3.3V PCI/PCI-X I/O

• Output impedance control on PCI-

X I/O for point-to-point or multi-

point connectivity

provides performance

enhancing features and is a

single chip solution that offers

the most economical component

cost savings.

• Multiple split read transaction

• Full byte-level parity protection

support on PCI-X

on internal data path and RAM

Applications

• No Snoop support in PCI/X

Communications

• Complete sequence segmentation

• Embedded Subsystems

• Disk Arrays

• SCSI Bridge

and reassembly done in hardware

• Eight GPIO pins per channel

• Loss of signal indication (per

channel) during internal SERDES

mode

• 64-bit addressing (44/45 bits per

Length/Address pair)

• High-performance Host Bus

• Interrupt optimization features

Adapters

• Frame payload size up to 2048

• Optional external boot ROM/

bytes

Flash (128K Bytes)

• Loop map, broadcast and bypass

• No external SRAM

support

12 3

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