HI-8282
ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER
September 2006
GENERALDESCRIPTION
FEATURES
! ARINC specification 429 compliant
! 16-Bit parallel data bus
The HI-8282 is a silicon gate CMOS device for interfacing
the ARINC 429 serial data bus to a 16-bit parallel data bus.
Two receivers and an independent transmitter are
provided. The receiver input circuitry and logic are
designed to meet theARINC 429 specifications for loading,
level detection, timing, and protocol. The transmitter
section provides the ARINC 429 communication protocol.
An external line driver such as the Holt HI-8585 or HI-3182
is required to translate the 5 volt logic outputs toARINC 429
drive levels.
! Direct receiver interface to ARINC bus
! Timing control 10 times the data rate
! Selectable data clocks
! Receiver error rejection per ARINC
specification 429
! Automatic transmitter data timing
! Self test mode
The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The data bus interfaces with
CMOS andTTL.
! Parity functions
! Low power, single 5 volt supply
! Industrial & full military temperature ranges
! DSCC SMD part number
Timing of all the circuitry begins with the master clock input,
CLK. For ARINC 429 applications, the master clock
frequency is 1 MHz.
PIN CONFIGURATION (Top View)
Each independent receiver monitors the data stream with a
sampling rate 10 times the data rate. The sampling rate is
software selectable at either 1MHz or 125KHz. The results
of a parity check are available as the 32nd ARINC bit. The
HI-8282 examines the null and data timings and will reject
erroneous patterns. For example, with a 125 KHz clock
selection, the data frequency must be between 10.4 KHz
and 15.6 KHz.
Vcc
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
NC
MR
(REC. 1 INPUT) 429DI1(A)
2
(MASTER RESET)
(REC.1 INPUT) 429DI1(B)
3
TX CLK (XMIT CLOCK OUT)
(REC. 2 INPUT) 429DI2(A)
4
CLK
NC
(MASTER CLK IN)
(REC. 2 INPUT) 429DI2(B)
5
(REC.1 DATA FLAG) D/R1
6
NC
(REC.2 DATA FLAG) D/R2
7
CWSTR (CONTROL WORD STROBE)
ENTX (ENABLE XMIT)
(REC. BYTE SELECT) SEL
8
The transmitter has a First In, First Out (FIFO) memory to
store 8ARINC words for transmission. The data rate of the
transmitter is software selectable by dividing the master
clock, CLK, by either 10 or 80. The master clock is used to
set the timing of theARINC transmission within the required
resolution.
(REC. 1 OUTPUT ENABLE) EN1
9
429DO (XMIT DATA)
429DO (XMIT DATA)
10
11
12
13
14
15
16
17
18
19
20
(REC. 2 OUTPUT ENABLE) EN2
TX/R
PL2
(XMIT READY FLAG)
BD15
BD14
BD13
BD12
BD11
BD10
BD09
BD08
BD07
BD06
(XMIT BYTE 2 LE)
(XMIT BYTE 1 LE)
PL1
BD00
BD01
BD02
BD03
BD04
BD05
GND
APPLICATIONS
! Avionics data communication
! Serial to parallel conversion
! Parallel to serial conversion
HI-8282C / CT / CM-01 / CM-03
SMD # 5962-8688002QA
40-Pin Ceramic Side-Brazed DIP
(See page 10 for additional Package Pin Configurations)
HOLT INTEGRATED CIRCUITS
www.holtic.com
(DS8282 Rev. E)
09/06