HI-1567, HI-1568
PIN DESCRIPTIONS
PIN
SYMBOL
FUNCTION
DESCRIPTION
1
2
VDDA
BUSA
BUSA
RXENA
GNDA
VDDB
BUSB
BUSB
RXENB
GNDB
RXB
power supply
analog output
analog output
digital input
power supply
power supply
analog output
analog output
digital input
power supply
digital output
digital output
digital input
digital input
digital input
digital output
digital output
digital input
digital input
digital input
+5 volt power for channel A
MIL-STD-1533 bus driver A, positive signal
MIL-STD-1553 bus driver A, negative signal
Receiver A enable. If low, forces RXA and RXA low (HI-1567) or High (HI-1568)
Ground for channel A
3
4
5
6
+5 volt power for channel B
7
MIL-STD-1533 bus driver B, positive signal
MIL-STD-1553 bus driver B, negative signal
Receiver B enable. If low, forces RXB and RXB low (HI-1567) or High (HI-1568)
Ground for channel B
8
9
10
11
12
13
14
15
16
17
18
19
15
Receiver B output, inverted
RXB
Receiver B outpot, non-invertedl
TXINHB
TXB
Transmit inhibit, channel B. If high BUSB, BUSB disabled
Transmitter B digital data input, non-inverted
Transmitter B digital data input, inverted
Receiver A output, inverted
TXB
RXA
RXA
Receiver A output, non-inverted
TXINHA
TXA
Transmit inhibit, channel A. If high BUSA, BUSA disabled
Transmitter A digital data input, non-inverted
Transmitter A digital data i nput, inverted
TXA
FUNCTIONAL DESCRIPTION
The HI-1567 family of data bus transceivers contain differ- The transmitter is automatically inhibited and placed in the
ential voltage source drivers and differential receivers. high impedance state when both TXA/B and TXA/B are ei-
They are intended for applications using a MIL-STD-1553 ther at a logic “1” or logic “0” simultaneously. A logic “1:” ap-
A/B data bus. The device produces a trapezoidal output plied to the TXINHA/B input will force the transmitter to the
waveform during transmission.
high impedance state, regardless of the state of TXA/B and
TXA/B
TRANSMITTER
RECEIVER
Data input to the transmitter section of these devices is
from the complimentary CMOS /TTL inputs TXA/B and The receiver is transformer coupled to the bus by a 1:1
TXA/B. This produces a nominal 30V peak to peak signal transformer. Its differential input stage drives a filter and
across a 140 ohm load. The transmitter is connected to the threshold comparator. CMOS/TTL data is outputted at the
bus via a 1:2.5 transformer whose secondary is connected RXA/B and RXA/B pins.
to two 52 ohm isolation resisters which feed the terminated
7 0 ohm bus. This will produce a nominal voltage on the bus The receiver outputs can both be forced to a logic "0"
of 7.5 volts peak to peak.
(HI-1567) or logic “1” (HI-1568) by setting RXENA or
RXENB low.
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