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HCPL-5200-200 PDF预览

HCPL-5200-200

更新时间: 2024-01-22 06:25:19
品牌 Logo 应用领域
惠普 - HP 光电
页数 文件大小 规格书
12页 296K
描述
Hermetically Sealed, Low IF, Wide VCC, Logic Gate Optocouplers

HCPL-5200-200 数据手册

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8
Typical Characteristics (cont’d.)  
All typical values are at T = 25°C, VCC = 5 V, IF(ON) = 5 mA, unless otherwise specified.  
A
Single Channel Product Only  
Parameter  
Symbol Typ.  
Units  
Test Conditions  
Fig. Notes  
Output Enable Time to Logic High  
tPZH  
tPZL  
tPHZ  
tPLZ  
30  
30  
45  
55  
ns  
8
Output Enable Time to Logic Low  
Output Disable Time from Logic High  
Output Disable Time from Logic Low  
ns  
ns  
ns  
8
8
8
Dual and Quad Channel Products Only  
RH = 45%, TA = 25°C,  
Input-Input Insulation Leakage Current  
II-I  
0.5  
nA  
V
I-I = 500 V, t = 5 s  
9
9
9
Resistance (Input-Input)  
RI-I  
1013  
VI-I = 500 V  
f = 1 MH  
Capacitance (Input-Input)  
CI-I  
1.5  
pF  
Notes:  
1. Peak Forward Input Current pulse width < 50 µs at 1 KHz maximum repetition rate.  
2. Each channel of a multichannel device.  
3. Duration of output short circuit time not to exceed 10 ms.  
4. All devices are considered two-terminal devices: measured between all input leads or terminals shorted together and all output leads  
or terminals shorted together.  
5. This is a momentary withstand test, not an operating condition.  
6. CML is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state (VO  
< 0.8 V). CM is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the logic  
high state (V H> 2.0 V).  
7. tPHL propagatOion delay is measured from the 50% point on the leading edge of the input pulse to the 1.3 V point on the leading edge  
of the output pulse. The t propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.3 V  
point on the trailing edgePoLHf the output pulse.  
8. Measured between each input pair shorted together and all output connections for that channel shorted together.  
9. Measured between adjacent input pairs shorted together for each multichannel device.  
10. Zero-bias capacitance measured between the LED anode and cathode.  
11. Standard parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD, Class H and Class K parts receive 100% testing at 25, 125,  
and –55°C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively).  
12. Parameters are tested as part of device initial characterization and after design and process changes. Parameters guaranteed to limits  
specified for all lots not specifically tested.  
Figure 1. Typical Logic Low Output  
Voltage vs. Temperature.  
Figure 2. Typical Logic High Output  
Current vs. Temperature.  

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