Datasheet > H5ANAG6NCMR-VKI

H5ANAG6NCMR-VKI

更新时间： 2023-12-06 20:10:56

品牌	Logo	应用领域
海力士 - HYNIX		双倍数据速率
页数	文件大小	规格书
42页	667K
描述
DDR4

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数据手册

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H5ANAG6NCMR-VKI 数据手册

Description

The H5ANAG6NCMR-xxI a 16Gb CMOS Double Data Rate IV (DDR4) Synchronous DRAM, ideally suited for

the main memory applications which requires large memory density and high bandwidth. SK hynix 8Gb

DDR4 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock.

While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK),

Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The

data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.

Device Features and Ordering Information

FEATURES

• VDD=VDDQ=1.2V +/- 0.06V

• Two Termination States such as RTT_PARK and

RTT_NOM switchable by ODT pin

• Fully differential clock inputs (CK, CK) operation

• Differential Data Strobe (DQS, DQS)

• Asynchronous RESET pin supported

• ZQ calibration supported

• On chip DLL align DQ, DQS and DQS transition with CK 

transition

• Write Levelization supported

• DM masks write data-in at the both rising and falling  • 8 bit pre-fetch

edges of the data strobe

• This product in compliance with the RoHS directive.

• All addresses and control inputs except data, data

strobes and data masks latched on the rising edges of

the clock

• Internal Vref DQ level generation is available

• Write CRC is supported at all speed grades

• Maximum Power Saving Mode is supported

• Programmable CAS latency 9, 10, 11, 12, 13, 14, 15,

16, 17, 18, 19 and 20 supported

• TCAR(Temperature Controlled Auto Refresh) mode is

supported

• Programmable CAS Write latency (CWL) = 9, 10, 11,

12, 14, 16, 18

• LP ASR(Low Power Auto Self Refresh) mode is sup-

ported

• Programmable burst length 4/8 with both nibble

sequential and interleave mode



• Fine Granularity Refresh is supported

• BL switch on the fly

• 16banks

• Per DRAM Addressability is supported

• Geardown Mode(1/2 rate, 1/4 rate) is supported

• Programable Preamble for read and write is supported

• Self Refresh Abort is supported

• AverageRefreshCycle (Tcaseof0 ^oC~95^oC)

- 7.8 µs at 0^oC ~ 85 ^oC

- 3.9 µs at 85^oC ~ 95 ^oC

• CA parity (Command/Address Parity) mode is sup-

ported

• Operating Temprerature Range

- Industrial Temperature (-40^oC ~ 95 ^oC)

• Bank Grouping is applied, and CAS to CAS latency

(tCCD_L, tCCD_S) for the banks in the same or different

bank group accesses are available

• JEDEC standard 96ball FBGA(x16)

• Driver strength selected by MRS

• Dynamic On Die Termination supported

Rev. 1.0 / Jan.2019

1 234 5 6 7...42

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