Datasheet > 传感器/换能器 > 图像传感器> FTF3020-M/HG

FTF3020-M/HG

更新时间： 2024-02-23 23:32:15

品牌	Logo	应用领域
恩智浦 - NXP		传感器图像传感器
页数	文件大小	规格书
16页	225K
描述
Full Frame CCD Image Sensor

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技术参数
数据手册

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FTF3020-M/HG 技术参数

是否Rohs认证：	符合	生命周期：	Contact Manufacturer
Reach Compliance Code：	unknown	风险等级：	5.61
水平像素：	3120	安装特点：	THROUGH HOLE MOUNT
最高工作温度：	60 °C	最低工作温度：	-40 °C
像素大小：	12X12 µm	子类别：	CCD Image Sensors
表面贴装：	NO	垂直像素：	2060
Base Number Matches：	1

FTF3020-M/HG 数据手册

Philips Semiconductors

Product specification

Full Frame CCD Image Sensor

FTF3020-M

Architecture of the FTF3020-M

The optical centres of all pixels in the image section form a square

grid. The charge is generated and integrated in this section. Output

registers are located below and above the image section for read-

out. After the integration time, the image charge is shifted one line

at the time to either the upper or lower register or to both

simultaneously, depending on the read-out mode. The left and the

right half of each register can be controlled independently. This

enables either single or multiple read-out. During vertical transport,

the C3 gates separate the pixels in the register.The central C3 gates

of the lower and upper registers are part of the left half of the sensor

(W and Z quadrants respectively). Each register can be used for

vertical binning. Each register contains a summing gate at both ends

that can be used for horizontal binning (see figure 2).

IMAGE SECTION

44.30 mm

Image diagonal (active video only)

Aspect ratio

Active image width x height

Pixel width x height

3:2

36.864 x 24.576 mm²

12x12 µm²

100%

Geometric fill factor

Image clock pins

Capacity of each clock phase

Number of active lines

16 pins (A1..A4)

7.5nF per pin

2048

Number of black reference lines

Number of dummy black lines

Total number of lines

4 (=2x2)

8 (=2x4)

2060

Number of active pixels per line

Number of overscan (timing) pixels per line

Number of black reference pixels per line

Total number of pixels per line

3072

8 (2x4)

40 (2x20)

3120

OUTPUT REGISTERS

Output buffers on each corner

Number of registers

Three-stage source follower

Number of dummy cells per register

Number of register cells per register

Output register horizontal transport clock pins

Capacity of each C-clock phase

Overlap capacity between neighbouring C-clocks

Output register Summing Gates

Capacity of each SG

14 (2x7)

3134 (3120+14)

6 pins per register (C1..C3)

200 pF per pin

40pF

4 pins (SG)

15pF

Reset Gate clock phases

Capacity of each RG

4 pins (RG)

15pF

1999 November

1 234 5 6 7...16

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