FTF3020-M

更新时间： 2024-01-25 15:49:38

品牌	Logo	应用领域
恩智浦 - NXP		传感器图像传感器
页数	文件大小	规格书
16页	225K
描述
Full Frame CCD Image Sensor

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技术参数
数据手册

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FTF3020-M 技术参数

是否Rohs认证：	符合	生命周期：	Contact Manufacturer
Reach Compliance Code：	unknown	风险等级：	5.61
水平像素：	3120	安装特点：	THROUGH HOLE MOUNT
最高工作温度：	60 °C	最低工作温度：	-40 °C
像素大小：	12X12 µm	子类别：	CCD Image Sensors
表面贴装：	NO	垂直像素：	2060
Base Number Matches：	1

FTF3020-M 数据手册

Philips Semiconductors

Product specification

Full Frame CCD Image Sensor

FTF3020-M

Specifications

ABSOLUTE MAXIMUM RATINGS¹

MIN.

MAX.

UNIT

GENERAL:

storage temperature

-55

-40

-20

-0.2

+80

+60

+20

+2.0

°C

µA

ambient temperature during operation

voltage between any two gates

DC current through any clock phase (absolute value)

OUT current (no short circuit protection)

VOLTAGES IN RELATION TO VPS:

VNS, SFD, RD

VCS, SFS

-0.5

-8

-5

+30

+25

all other pins

VOLTAGES IN RELATION TO VNS:

SFD, RD

VCS, SFS, VPS

-15

-30

+0.5

all other pins

DC CONDITIONS²

MIN. [V]

TYPICAL [V]

MAX. [V]

MAX. [mA]

4.5

VNS³

VPS

SFD

SFS

VCS

N substrate

P substrate

6.5

15.5

Source Follower Drain

Source Follower Source

Current Source

Output Gate

-5

Reset Drain

AC CLOCK LEVEL CONDITIONS²

MIN.

TYPICAL

MAX.

UNIT

IMAGE CLOCKS:

A-clock amplitude during integration and hold

A-clock amplitude during vertical transport (duty cycle=5/8)⁴

A-clock low level

Charge Reset (CR) level on A-clock ⁵

-5

OUTPUT REGISTER CLOCKS:

C-clock amplitude (duty cycle during hor. transport = 3/6)

C-clock low level

Summing Gate (SG) amplitude

Summing Gate (SG) low level

4.75

5.25

3.5

OTHER CLOCKS:

Reset Gate (RG) amplitude

Reset Gate (RG) low level

Charge Reset (CR) pulse on Nsub

¹During Charge Reset it is allowed to exceed maximum rating levels (see note ⁵).

²All voltages in relation to SFS.

³To set the VNS voltage for optimal Vertical Anti-Blooming (VAB), it should be adjustable between minimum and maximum values.

⁴Three-level clock is preferred for maximum charge; the swing during vertical transport should be 4V higher than the voltage during integration.

A two level clock (typically 10V) can be used if a lower maximum charge handling capacity is allowed.

⁵Charge Reset can be achieved in two ways:

• The typical A-clock low level is applied to all image clocks; for proper CR, an additional Charge Reset pulse on VNS is required (preferred).

• The typical CR level is applied to all image clocks simultaneously.

1999 November

1 2 3 456 7 8...16

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