Revision 5
ex Automotive Family FPGAs
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Live on Power-Up
Specifications
No Power-Up/Down Sequence Required for Supply
Voltages
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3,000 to 12,000 Available System Gates
Maximum 512 Flip-Flops (Using CC Macros)
0.22 μm CMOS Process Technology
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Configurable Weak Resistor Pull-Up or Pull-Down for
Tristated Outputs during Power-Up
Up to 132 User-Programmable I/O Pins
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Individual Output Slew-Rate Control
2.5 V and 3.3 V I/Os
Software Design Support with Designer and Libero®
Features
Integrated Design Environment (IDE) Tools
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250 MHz Internal Performance, Low-Power Antifuse
FPGA
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Up to 100% Resource Utilization with 100% Pin Locking
Deterministic Timing
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Advanced Small-Footprint Packages
Unique In-System Diagnostic and Verification Capability
with Silicon Explorer II
Pin-to-Pin Compatibility with eX Commercial- and
Industrial-Grade Devices
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Boundary Scan Testing in Compliance with IEEE
Standard 1149.1 (JTAG)
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Hot-Swap Compliant I/Os
Single-Chip Solution
Nonvolatile
FuseLock™ Secure Programming Technology Designed
to Prevent Reverse Engineering and Design Theft
Product Profile
Device
eX64
eX128
eX256
Capacity
3,000
2,000
6,000
4,000
12,000
8,000
System Gates
Typical Gates
Register Cells
Dedicated Flip-Flops
Maximum Flip-Flops
64
128
128
256
256
512
Combinatorial Cells
Maximum User I/Os
128
84
256
100
512
132
Global Clocks
Hardwired
Routed
1
2
1
2
1
2
Speed Grades*
Std.
A
Std.
A
Std.
A
Temperature Grades*
Package (by pin count)
TQ
CS
64, 100
49, 128
64, 100
49, 128
100
128, 180
Note: * The eX family is also offered in commercial and industrial temperature grades with –F, –P, and Std. speed grades. Refer to
the eX Family FPGAs datasheet for more details.
October 2012
i
© 2012 Microsemi Corporation