Data Sheet
ADF7021
SPECIFICATIONS
VDD = 2.3 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3 V, TA = 25°C.
All measurements are performed with the EVAL-ADF7021DBx using the PN9 data sequence, unless otherwise noted.
RF AND PLL SPECIFICATIONS
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
RF CHARACTERISTICS
See Table 9 for required VCO_BIAS and
VCO_ADJUST settings
Frequency Ranges (Direct Output)
160
862
80
650
950
325
475
MHz
MHz
MHz
MHz
External inductor VCO
Internal inductor VCO
External inductor VCO, RF divide-by-2 enabled
Internal inductor VCO, RF divide-by-2 enabled
Crystal reference/external reference
Frequency Ranges (RF Divide-by-2 Mode)
431
Phase Frequency Detector (PFD) Frequency1 RF/256
26/30 MHz
PHASE-LOCKED LOOP (PLL)
VCO Gain2
868 MHz, Internal Inductor VCO
434 MHz, Internal Inductor VCO
426 MHz, External Inductor VCO
160 MHz, External Inductor VCO
Phase Noise (In-Band)
58
29
27
6
MHz/V VCO_ADJUST = 0, VCO_BIAS = 8
MHz/V VCO_ADJUST = 0, VCO_BIAS = 8
MHz/V VCO_ADJUST = 0, VCO_BIAS = 3
MHz/V VCO_ADJUST = 0, VCO_BIAS = 2
868 MHz, Internal Inductor VCO
−97
dBc/Hz 10 kHz offset, PA = 10 dBm, VDD = 3.0 V,
PFD = 19.68 MHz, VCO_BIAS = 8
433 MHz, Internal Inductor VCO
426 MHz, External Inductor VCO
Phase Noise (Out-of-Band)
−103
−95
dBc/Hz 10 kHz offset, PA = 10 dBm, VDD = 3.0 V,
PFD = 19.68 MHz, VCO_BIAS = 8
dBc/Hz 10 kHz offset, PA = 10 dBm, VDD = 3.0 V,
PFD = 9.84 MHz, VCO_BIAS = 3
−124
dBc/Hz 1 MHz offset, fRF = 433 MHz, PA = 10 dBm,
V
DD = 3.0 V, PFD = 19.68 MHz, VCO_BIAS = 8
Normalized In-Band Phase Noise Floor3
PLL Settling
−203
40
dBc/Hz
µs
Measured for a 10 MHz frequency step to within
5 ppm accuracy, PFD = 19.68 MHz, loop
bandwidth (LBW) = 100 kHz
REFERENCE INPUT
Crystal Reference4
External Oscillator4, 5
Crystal Start-Up Time6
XTAL Bias = 20 µA
XTAL Bias = 35 µA
Input Level for External Oscillator7
OSC1
3.625
3.625
26
30
MHz
MHz
0.930
0.438
ms
ms
10 MHz XTAL, 33 pF load capacitors, VDD = 3.0 V
10 MHz XTAL, 33 pF load capacitors, VDD = 3.0 V
0.8
CMOS levels
V p-p
V
Clipped sine wave
OSC2
ADC PARAMETERS
INL
DNL
0.4
0.4
LSB
LSB
VDD = 2.3 V to 3.6 V, TA = 25°C
VDD = 2.3 V to 3.6 V, TA = 25°C
1 The maximum usable PFD at a particular RF frequency is limited by the minimum N divide value.
2 VCO gain measured at a VCO tuning voltage of 1 V. The VCO gain varies across the tuning range of the VCO. The software package ADIsimPLL™ can be used to model this
variation.
3 This value can be used to calculate the in-band phase noise for any operating frequency. Use the following equation to calculate the in-band phase noise performance
as seen at the PA output: −203 + 10 log(fPFD) + 20 logN.
4 Guaranteed by design. Sample tested to ensure compliance.
5 A TCXO, VCXO, or OCXO can be used as an external oscillator.
6 Crystal start-up time is the time from chip enable (CE) being asserted to correct clock frequency on the CLKOUT pin.
7 Refer to the Reference Input section for details on using an external oscillator.
Rev. B | Page 5 of 64
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