Data Sheet
ADF7020
Parameter
Min
Typ
Max
Unit
Test Conditions
REFERENCE INPUT
Crystal Reference
External Oscillator
Load Capacitance
Crystal Start-Up Time
3.625
3.625
24
24
MHz
MHz
pF
ms
33
2.1
1.0
See crystal manufacturer’s specification sheet
11.0592 MHz crystal, using 33 pF load capacitors
Using 16 pF load capacitors
ms
Input Level
CMOS levels
See the Reference Input section
ADC PARAMETERS
INL
DNL
1
1
LSB
LSB
From 2.3 V to 3.6 V, TA = 25°C
From 2.3 V to 3.6 V, TA = 25°C
TIMING INFORMATION
Chip Enabled to Regulator Ready
Chip Enabled to RSSI Ready
Tx to Rx Turnaround Time
10
3.0
µs
ms
CREG = 100 nF
See Table 11 for more details
Time to synchronized data out, includes AGC settling;
see the AGC Information and Timing section
150 µs +
(5 × TBIT)
LOGIC INPUTS
Input High Voltage, VINH
0.7 ×
VDD
V
V
Input Low Voltage, VINL
0.2 ×
VDD
Input Current, IINH/IINL
Input Capacitance, CIN
Control Clock Input
LOGIC OUTPUTS
1
10
50
µA
pF
MHz
Output High Voltage, VOH
DVDD −
0.4
V
IOH = 500 µA
IOL = 500 µA
Output Low Voltage, VOL
CLKOUT Rise/Fall
CLKOUT Load
0.4
5
10
+85
V
ns
pF
°C
TEMPERATURE RANGE, TA
POWER SUPPLIES
Voltage Supply
−40
2.3
VDD
3.6
V
All VDD pins must be tied together
Transmit Current Consumption
FRF = 915 MHz, VDD = 3.0 V,
PA is matched to 50 Ω
−20 dBm
−10 dBm
0 dBm
14.8
15.9
19.1
28.5
26.8
mA
mA
mA
mA
mA
Combined PA and LNA matching network as on
EVAL-ADF7020DBZx boards
VCO_BIAS_SETTING = 12
10 dBm
10 dBm
PA matched separately with external antenna
switch, VCO_BIAS_SETTING = 12
Receive Current Consumption
Low Current Mode
High Sensitivity Mode
Power-Down Mode
19
21
mA
mA
Low Power Sleep Mode
0.1
1
µA
1 Higher data rates are achievable, depending on local regulations.
2 For the definition of frequency deviation, see the Register 2—Transmit Modulation Register (FSK Mode) section.
3 For the definition of GFSK frequency deviation, see the Register 2—Transmit Modulation Register (GFSK/GOOK Mode) section.
4 Measured as maximum unmodulated power. Output power varies with both supply and temperature.
5 For matching details, see the LNA/PA Matching section and the AN-764 Application Note.
6 Sensitivity for combined matching network case is typically 2 dB less than separate matching networks.
7 See Table 5 for a description of different receiver modes.
8 Follow the matching and layout guidelines to achieve the relevant FCC/ETSI specifications.
Rev. D | Page 7 of 48