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EPM7256BFC100-10 PDF预览

EPM7256BFC100-10

更新时间: 2023-08-15 00:00:00
品牌 Logo 应用领域
阿尔特拉 - ALTERA /
页数 文件大小 规格书
147页 3309K
描述
EE PLD, 10ns, 256-Cell, CMOS, PBGA100, FINE LINE, BGA-100

EPM7256BFC100-10 数据手册

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MAX 7000B  
Programmable Logic  
Device Family  
®
October 2000, ver. 2.1  
Data Sheet  
High-performance 2.5-V CMOS EEPROM-based programmable  
logic devices (PLDs) built on second-generation Multiple Array  
MatriX (MAX®) architecture (see Table 1)  
Features...  
Pin-compatible with the popular 5.0-V MAX 7000S and 3.3-V  
MAX 7000A device families  
High-density PLDs ranging from 600 to 10,000 usable gates  
3.5-ns pin-to-pin logic delays with counter frequencies in excess  
of 285.7 MHz  
Preliminary  
Information  
Advanced 2.5-V in-system programmability (ISP)  
Programs through the built-in IEEE Std. 1149.1 Joint Test Action  
Group (JTAG) interface with advanced pin-locking capability  
Enhanced ISP algorithm for faster programming  
ISP_Done bit to ensure complete programming  
Pull-up resistor on I/O pins during in-system programming  
ISP circuitry compliant with IEEE Std. 1532  
For information on in-system programmable 5.0-V MAX 7000S or 3.3-V  
MAX 7000A devices, see the MAX 7000 Programmable Logic Device Family  
Data Sheet or the MAX 7000A Programmable Logic Device Family Data Sheet.  
f
Table 1. MAX 7000B Device Features  
Note (1)  
Feature  
EPM7032B  
EPM7064B  
EPM7128B  
EPM7256B  
EPM7512B  
Usable gates  
Macrocells  
600  
32  
2
1,250  
64  
2,500  
128  
8
5,000  
256  
16  
10,000  
512  
Logic array blocks  
4
32  
Maximum user I/O  
pins  
36  
68  
100  
164  
212  
t
t
t
t
f
(ns)  
(ns)  
3.5  
2.3  
3.5  
2.3  
4.0  
2.8  
5.0  
3.5  
6.0  
3.9  
PD  
SU  
(ns)  
1.0  
1.0  
1.0  
1.0  
1.0  
FSU  
CO1  
CNT  
(ns)  
2.3  
2.3  
2.8  
3.5  
3.7  
(MHz)  
285.7  
285.7  
238.1  
188.7  
163.9  
Note:  
(1) Contact Altera for up-to-date information on timing information.  
Altera Corporation  
1
A-DS-MAX7000B-02.1  

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