Datasheet > EPF10K10ATC100-1N

EPF10K10ATC100-1N

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
英特尔 - INTEL		/
页数	文件大小	规格书
143页	1990K
描述
Loadable PLD, 0.5ns, CMOS, PQFP100, TQFP-100

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

EPF10K10ATC100-1N 数据手册

浏览型号EPF10K10ATC100-1N的Datasheet PDF文件第2页

浏览型号EPF10K10ATC100-1N的Datasheet PDF文件第3页

浏览型号EPF10K10ATC100-1N的Datasheet PDF文件第4页

浏览型号EPF10K10ATC100-1N的Datasheet PDF文件第6页

浏览型号EPF10K10ATC100-1N的Datasheet PDF文件第7页

浏览型号EPF10K10ATC100-1N的Datasheet PDF文件第8页

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Notes to tables:

(1) FLEX 10K and FLEX 10KA device package types include plastic J-lead chip carrier (PLCC), thin quad flat pack

(TQFP), plastic quad flat pack (PQFP), power quad flat pack (RQFP), ball-grid array (BGA), pin-grid array (PGA),

and FineLine BGA^TMpackages.

(2) This option is supported with a 256-pin FineLine BGA package. By using SameFrame pin migration, all FineLine

BGA packages are pin compatible. For example, a board can be designed to support both 256-pin and 484-pin

FineLine BGA packages. The Altera software automatically avoids conflicting pins when future migration is set.

Altera’s FLEX 10K devices are the industry’s first embedded PLDs. Based

on reconfigurable CMOS SRAM elements, the Flexible Logic Element

General

Description

MatriX (FLEX) architecture incorporates all features necessary to

implement common gate array megafunctions. With up to 250,000 gates,

the FLEX 10K family provides the density, speed, and features to integrate

entire systems, including multiple 32-bit buses, into a single device.

FLEX 10K devices are reconfigurable, which allows 100% testing prior to

shipment. As a result, the designer is not required to generate test vectors

for fault coverage purposes. Additionally, the designer does not need to

manage inventories of different ASIC designs; FLEX 10K devices can be

configured on the board for the specific functionality required.

Table 6 shows FLEX 10K performance for some common designs. All

performance values were obtained with Synopsys DesignWare or LPM

functions. No special design technique was required to implement the

applications; the designer simply inferred or instantiated a function in a

Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or

schematic design file.

Table 6. FLEX 10K & FLEX 10KA Performance

Application

Resources

Used

Performance

Units

LEs EABs

-1 Speed

Grade

-2 Speed

Grade

-3 Speed

Grade

-4 Speed

Grade

16-bit loadable

204

166

125

MHz

counter (1)

16-bit accumulator (1) 16

16-to-1 multiplexer (2) 10

204

4.2

166

5.8

125

6.0

7.0

MHz

256 × 8 RAM read

cycle speed (3)

172

145

108

MHz

256 × 8 RAM write

cycle speed (3)

106

MHz

Notes:

(1) The speed grade of this application is limited because of clock high and low specifications.

(2) This application uses combinatorial inputs and outputs.

(3) This application uses registered inputs and outputs.

Altera Corporation

1 2 3 456 7 8...143

下载PDF

与EPF10K10ATC100-1N相关器件

型号	品牌	描述	获取价格	数据表
EPF10K10ATC100-3	INTEL	Loadable PLD, 0.8ns, CMOS, PQFP100, TQFP-100	获取价格
EPF10K10ATC100-3	ALTERA	Loadable PLD, 0.8ns, CMOS, PQFP100, TQFP-100	获取价格
EPF10K10ATC144-1	INTEL	Loadable PLD, 0.5ns, CMOS, PQFP144, TQFP-144	获取价格
EPF10K10ATC144-2	ALTERA	Loadable PLD, 0.6ns, CMOS, PQFP144, TQFP-144	获取价格
EPF10K10ATC144-2N	ALTERA	Loadable PLD, 0.6ns, CMOS, PQFP144, TQFP-144	获取价格
EPF10K10ATC144-3	ALTERA	Embedded Programmable Logic Device Family	获取价格