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EP3SE260F1517I3N PDF预览

EP3SE260F1517I3N

更新时间: 2024-01-30 12:49:56
品牌 Logo 应用领域
阿尔特拉 - ALTERA 时钟可编程逻辑
页数 文件大小 规格书
16页 191K
描述
Field Programmable Gate Array, 717MHz, 255000-Cell, CMOS, PBGA1517, LEAD FREE, FBGA-1517

EP3SE260F1517I3N 技术参数

是否Rohs认证: 符合生命周期:End Of Life
包装说明:BGA, BGA1517,39X39,40Reach Compliance Code:compliant
ECCN代码:3A001.A.7.AHTS代码:8542.39.00.01
风险等级:5.18其他特性:IT CAN ALSO OPERATE FROM 1.05 TO 1.15V SUPPLY
最大时钟频率:717 MHzJESD-30 代码:S-PBGA-B1517
长度:40 mm输入次数:976
逻辑单元数量:255000输出次数:976
端子数量:1517封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA1517,39X39,40
封装形状:SQUARE封装形式:GRID ARRAY
电源:1.2/3.3 V可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
认证状态:Not Qualified座面最大高度:3.9 mm
子类别:Field Programmable Gate Arrays最大供电电压:0.94 V
最小供电电压:0.86 V标称供电电压:0.9 V
表面贴装:YES技术:CMOS
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM宽度:40 mm
Base Number Matches:1

EP3SE260F1517I3N 数据手册

 浏览型号EP3SE260F1517I3N的Datasheet PDF文件第2页浏览型号EP3SE260F1517I3N的Datasheet PDF文件第3页浏览型号EP3SE260F1517I3N的Datasheet PDF文件第4页浏览型号EP3SE260F1517I3N的Datasheet PDF文件第5页浏览型号EP3SE260F1517I3N的Datasheet PDF文件第6页浏览型号EP3SE260F1517I3N的Datasheet PDF文件第7页 
1. Stratix III Device Family Overview  
SIII51001-1.8  
The Stratix® III family provides one of the most architecturally advanced,  
high-performance, low-power FPGAs in the marketplace.  
Stratix III FPGAs lower power consumption through Altera’s innovative  
Programmable Power Technology, which provides the ability to turn on the  
performance where needed and turn down the power consumption for blocks not in  
use. Selectable Core Voltage and the latest in silicon process optimizations are also  
employed to deliver the industry’s lowest power, high-performance FPGAs.  
Specifically designed for ease of use and rapid system integration, the Stratix III  
FPGA family offers two variants optimized to meet different application needs:  
The Stratix III L family provides balanced logic, memory, and multiplier ratios for  
mainstream applications.  
The Stratix III E family is memory- and multiplier-rich for data-centric  
applications.  
Modular I/O banks with a common bank structure for vertical migration lend  
efficiency and flexibility to the high-speed I/O. Package and die enhancements with  
dynamic on-chip termination, output delay, and current strength control provide  
best-in-class signal integrity.  
Based on a 1.1-V, 65-nm all-layer copper SRAM process, the Stratix III family is a  
programmable alternative to custom ASICs and programmable processors for  
high-performance logic, digital signal processing (DSP), and embedded designs.  
Stratix III devices include optional configuration bit stream security through volatile  
or non-volatile 256-bit Advanced Encryption Standard (AES) encryption. Where  
ultra-high reliability is required, Stratix III devices include automatic error detection  
circuitry to detect data corruption by soft errors in the configuration random-access  
memory (CRAM) and user memory cells.  
Features Summary  
Stratix III devices offer the following features:  
48,000 to 338,000 equivalent logic elements (LEs) ( refer to Table 1–1)  
2,430 to 20,497 Kbits of enhanced TriMatrix memory consisting of three RAM  
block sizes to implement true dual-port memory and FIFO buffers  
High-speed DSP blocks provide dedicated implementation of 9×9, 12×12, 18×18,  
and 36×36 multipliers (at up to 550 MHz), multiply-accumulate functions, and  
finite impulse response (FIR) filters  
I/O:GND:PWR ratio of 8:1:1 along with on-die and on-package decoupling for  
robust signal integrity  
Programmable Power Technology, which minimizes power while maximizing  
device performance  
© March 2010 Altera Corporation  
Stratix III Device Handbook, Volume 1  

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