ENC424J600/624J600
Communication
with
the
microcontroller
is
1.0
DEVICE OVERVIEW
implemented via the SPI or parallel interface, with data
rates ranging from 14 Mbit/s (SPI) to 160 Mbit/s
(demultiplexed, 16-bit parallel interface). Dedicated
pins are used for LED link and activity indication and for
transmit/receive/DMA interrupts.
This document contains device-specific information for
the following devices:
• ENC424J600
• ENC624J600
A generous 24-Kbyte on-chip RAM buffer is available
for TX and RX operations. It may also be used by the
host microcontroller for general purpose storage.
Communication protocols, such as TCP, can use this
memory for saving data which may need to be
retransmitted.
The ENC424J600 and ENC624J600 are stand-alone,
Fast Ethernet controllers with an industry standard
Serial Peripheral Interface (SPI) or a flexible parallel
interface. They are designed to serve as an Ethernet
network interface for any microcontroller equipped with
SPI or a standard parallel port.
For easy end product manufacturability, each
ENC624J600 family device is preprogrammed with a
unique nonvolatile MAC address. In most cases, this
ENC424J600/624J600 devices meet all of the
IEEE 802.3 specifications applicable to 10Base-T and
100Base-TX Ethernet, including many optional
clauses, such as auto-negotiation. They incorporate a
number of packet filtering schemes to limit incoming
packets. They also provide an internal, 16-bit wide
DMA for fast data throughput and support for hardware
IP checksum calculations.
allows the end device to avoid
programming step.
a
serialized
The only functional difference between the
ENC424J600 (44-pin) and ENC624J600 (64-pin)
devices are the number of parallel interface options
they support. These differences, along with a summary
of their common features, are provided in Table 1-1. A
general block diagram for the devices is shown in
Figure 1-1.
For applications that require the security and authenti-
cation features of SSL, TLS and other protocols related
to cryptography, a block of security engines is provided.
The engines perform RSA, Diffie-Hellman, AES, MD5
and SHA-1 algorithm computations, allowing reduced
code size, faster connection establishment and
throughput, and reduced firmware development effort.
A list of the pin features, sorted by function, is
presented in Table 1-2.
TABLE 1-1:
DEVICE FEATURES FOR ENC424J600/624J600
Feature ENC424J600
44
ENC624J600
Pin Count
64
Ethernet Operating Speed
Ethernet Duplex Modes
Ethernet Flow Control
Buffer Memory (bytes)
Internal Interrupt Sources
Serial Host Interface (SPI)
Parallel Host Interface:
Operating modes
10/100 Mbps (auto-negotiate, auto-sense or manual)
Half and Full (auto-negotiate and manual)
Pause and Backpressure (auto and manual)
24K (organized as 12K word x 16)
11 (mappable to a single external interrupt flag)
Yes
Yes
2
8
Muliplexed,
8-bit
Yes
No
No
No
Yes
Yes
Yes
Yes
16-bit
Demultiplexed, 8-bit
16-bit
Cryptographic Security Options:
AES, 128/192/256-bit
MD5/SHA-1
Yes
Yes
Yes
Yes
Yes
Yes
Modular Exponentiation, 1024-bit
Receive Filter Options
Accept or reject packets with CRC match/mismatch, runt error collect
or reject, Unicast, Not-Me Unicast, Multicast, Broadcast,
Magic Packet™, Pattern Table and Hash Table
Packages
44-Pin TQFP, QFN
64-Pin TQFP
2010 Microchip Technology Inc.
DS39935C-page 5