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EN23F0QI PDF预览

EN23F0QI

更新时间: 2024-02-05 20:13:29
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ENPIRION /
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26页 1852K
描述
15A Voltage Mode Synchronous Buck PWM

EN23F0QI 数据手册

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EN23F0QI  
Pin Description  
I/O Legend:  
P=Power  
G=Ground  
NC=No Connect  
I=Input O=Output  
I/O=Input/Output  
PIN  
NAME I/O  
FUNCTION  
NO CONNECT – These pins may be internally connected. Do not connect them to each  
1-24,  
36, 81  
NC  
NC other or to any other electrical signal. Failure to follow this guideline may result in device  
damage.  
Regulated converter output. Connect these pins to the load and place output capacitor  
between these pins and PGND pins 40-42.  
25-35  
VOUT  
O
NO CONNECT – These pins are internally connected to the common switching node of the  
NC(SW) NC internal MOSFETs. They are not to be electrically connected to any external signal, ground,  
or voltage. Failure to follow this guideline may result in damage to the device.  
37-39,  
83-92  
Input/Output power ground. Connect these pins to the ground electrode of the input and  
40-46  
47-63  
PGND  
PVIN  
G
P
output filter capacitors. See VOUT and PVIN pin descriptions for more details.  
Input power supply. Connect to input power supply. Decouple with input capacitor to PGND  
pins 43-46.  
Internal 3.3V linear regulator output. Connect this pin to AVIN (Pin 73) for applications  
where operation from a single input voltage (PVIN) is required. If AVINO is being used,  
place a 1µF, X5R/X7R, capacitor between AVINO and AGND as close as possible to  
AVINO.  
64  
AVINO  
O
65  
66  
PG  
BTMP  
I/O Place a 0.1µF, X7R, capacitor between this pin and BTMP.  
I/O See pin 65 description.  
Internal regulated voltage used for the internal control circuitry. Place a 1µF, X7R, capacitor  
between this pin and BGND.  
See pin 67 description.  
Digital Input. This pin accepts either an input clock to phase lock the internal switching  
frequency or a S_OUT signal from another EN23F0QI. Leave this pin floating if not used.  
Digital Output. PWM signal is output on this pin. Leave this pin floating if not used.  
Power OK is an open drain transistor (pulled up to AVIN or similar voltage) used for power  
system state indication. POK is logic high when VOUT is -10% of VOUT nominal. Leave  
this pin floating if not used.  
67  
68  
69  
70  
VDDB  
BGND  
S_IN  
O
G
I
S_OUT  
O
71  
POK  
O
Input Enable. Applying a logic high to this pin enables the output and initiates a soft-start.  
Applying a logic Low disables the output. Do not leave this pin floating.  
3.3V Input power supply for the controller. Place a 0.1µF, X7R, capacitor between AVIN  
and AGND.  
Analog Ground. This is the ground return for the controller. Needs to be connected to a  
quiet ground.  
72  
73  
74  
75  
ENABLE  
AVIN  
I
P
G
I
AGND  
M/S  
A logic level low configures the device as Master and a logic level high configures the  
device as a Slave. Connect to ground in standalone mode.  
External Feedback Input. The feedback loop is closed through this pin. A voltage divider at  
76  
77  
78  
VFB  
EAIN  
SS  
I/O VOUT is used to set the output voltage. The mid-point of the divider is connected to VFB. A  
phase lead capacitor from this pin to VOUT is also required to stabilize the loop.  
Optional Error Amplifier Input. Allows for customization of the control loop for performance  
optimization. Leave this pin floating if unused.  
O
Soft-Start node. The soft-start capacitor is connected between this pin and AGND. The  
I/O value of this capacitor determines the startup time. See Soft-Start Operation in the  
Functional Description section for details.  
Programmable over-current protection. Placement of a resistor on this pin will adjust the  
over-current protection threshold. See Table 2 for the recommended RCLX Value to set  
OCP at the nominal value specified in the Electrical Characteristics table. No current limit  
79  
RCLX  
I/O  
protection when this pin is left floating.  
Adding a resistor (RFS) to this pin will adjust the switching frequency of the EN23F0QI. See  
I/O Table 1 for suggested resistor values on RFS for various PVIN/VOUT combinations to  
maximize efficiency. Do not leave this pin floating.  
80  
FADJ  
82  
93  
CGND  
PGND  
G
Connect to GND plane at all times.  
Not a perimeter pin. Device thermal pad to be connected to the system GND plane for heat-  
sinking purposes.  
G
©Enpirion 2012 all rights reserved, E&OE  
Enpirion Confidential  
www.enpirion.com, Page 3  

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