EL2166
Open-Loop DC Electrical Specifications
V
= ±15V, R = 150Ω, T = 25°C unless otherwise specified (Continued)
S
L
A
LIMITS
TYP
70
PARAMETER
DESCRIPTION
CONDITIONS
TEMP
25°C
25°C
MIN
MAX
UNITS
µA
I
I
, ON
DISABLE Pin Input Current, Pin 8 = +5V
DISABLE Pin Input Current, Pin 8 = 0V
150
DIS
, OFF
-150
-60
µA
DIS
NOTES:
1. Measured from T
to T
.
MAX
MIN
= ±12.6V for V = ±15V and T = 25°C. V
2. V
= ±2.6V for V = ±5V and T = 25°C.
S A
CM
3. The supplies are moved from ±5V to ±15V.
4. V = ±7V for V = ±15V, and V = ±2V for V = ±5V.
S
A
CM
OUT OUT
S
S
5. A heat sink is required to keep junction temperature below absolute maximum when an output is shorted.
6. The EL2166 will remain ENABLED if pin 8 is either left unconnected or VIH is applied to pin 8.
Closed-Loop AC Electrical Specifications
V
= ±15V, A = +2, R = 560Ω, R = 150Ω, T = 25°C unless otherwise noted
S
V
F
L
A
LIMITS
TYP
110
115
95
PARAMETER
BW
DESCRIPTION
CONDITIONS
MIN
MAX
UNITS
MHz
MHz
MHz
MHz
V/µs
ns
-3dB Bandwidth (Note 1)
V
= ±15V, A = +2
S
S
S
S
V
V
V
V
= ±15V, A = +1
V
= ±5V, A = +2
V
= ±5V, A = +1
V
100
1500
3.2
SR
t , t
Slew Rate (Note 1)(Note 2)
Rise Time, Fall Time (Note 1)
Propagation Delay (Note 1)
Overshoot (Note 1)
R
= 400Ω
1000
L
V
= ±500mV
R
F
OUT
t
4.3
ns
PD
OS
V
V
A
= ±500mV
= ±10V
7
%
OUT
OUT
t
0.1% Settling Time (Note 1)
35
ns
S
= ±1, R = 1k
V
L
dG
Differential Gain (Note 1)(Note 3)
Differential Phase (Note 1)(Note 3)
Disable/Enable Time (Note 4)
R = 150Ω, V = ±15V
0.025
0.05
0.01
0.01
0.04
0.02
0.01
0.01
75
%
%
L
S
R = 150Ω, V = ±5V
L
S
R = 500Ω, V = ±15V
%
L
S
R = 500Ω, V = 5V
%
L
S
dP
R = 150Ω, V = ±15V
deg (°)
deg (°)
deg (°)
deg (°)
ns
L
S
R = 150Ω, V = ±5V
L
S
R = 500Ω, V = ±15V
L
S
R = 500Ω, V = 5V
L
S
t
DIS
NOTES:
1. All AC tests are performed on a “warmed up” part, except for Slew Rate, which is pulse tested.
2. Slew Rate is with V from +10V to -10V and measured at the 25% and 75% points.
OUT
3. DC offset from -0.714V through +0.714V, AC amplitude 286 mV
, f = 3.58MHz.
P-P
4. Disable/Enable time is defined as the time from when the logic signal is applied to the DISABLE pin to when the output voltage has gone 50%
of the way from its initial to its final value.
3