Ei68C681
Ei88C681
DUAL UART
Semiconductor, Inc.
FEATURES
DESCRIPTION
The Epic Ei88C681/Ei68C681 DUART Dual Universal
Asynchronous Receiver and Transmitter is a data com-
munication device that provides two fully independent full
duplex asynchronous communication channels in a
single package. The DUART is designed for use in
microprocessor based systems and may be used in a
polled or interrupt driven environment.
•
Full duplex, dual channel asynchronous
receiver and transmitter
•
•
•
•
Quadruple-buffered receiver and transmitter
Stop bits programmable in 1/16-bit increments
Internal bit rate generator with 23 bit rates
Two basic versions of the DUART are available, each
optimized for use with various microprocessor families:
the 88C81 for 8085/85, 8080/88, Z80, Z8000, 68XX and
65XX family based systems., and the 68C681 for 68000
family based systems. A programmable mode of the
Ei88C681 versions provides an interrupt daisy chain for
use in Z80 and Z8000 based systems. The bus inter-
faces are however general enough to allow interfacing
with other microprocessors and microcontrollers. The
88C681 and 68C681 are enhanced versions of the
Signetics 2681 and the Motorola 68681, and are pin and
function compatible with those devices. Each channel of
the DUART may be independently programmed for
operating mode and data format. The operating speed of
each receiver and transmitter can beselected from baud
rate generator, from the multi-purpose on chip
counter/timer or from an external 1 x or 16 x clock.The bit
rate generator can operate directly from a crystal connect-
ed across two pins or from an external clock. The ability to
independently program the operating speed of the receiv-
er and transmitter of each channel makes the DUART
attractive for split-speed channel application such as clus-
tered terminal systems. Both receive and transmit data is
quadruple-buffered in on-chip FIFO to minimize the risk of
receiver overrun or to reduce overhead in interrupt-drive
applications.
Independent bit rate selection for each Rx
and Tx
•
•
Maximum bit rate: 1 x clock - 2 Mb/sec., 16
x clock- 250 Kb/sec.
Normal, auto-echo, local loop-back and
remote loop-back modes
•
•
Multi-function 16-bit counter/timer
Interrupt output with 8 maskable interrupt
ing conditions
•
•
•
Interrupt vector output on acknowledge
Programmable interrupt daisy chain
Up to 15 I/O pins (depending on package
and version)
•
Multidrop mode compatible with 8051 nine-
bit mode
•
•
•
On-chip oscillator for crystal
Stand-by mode to reduce operating power
Advanced CMOS low power technology
PIN CONFIGURATION
Part Numbers May Be Marked With "IMP" or "Ei."
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
A1
IP3
A2
IP1
A3
A0
IP3
A1
IP1
A2
VCC
IP4
IP5
IACK•
IP2
CS•
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
IP4/IEI
IP5/IEO
IP6/IACKN
IP2
CEN
RESET
X2
X1/CLK
RxDA
TxDA
OP0
OP2
OP4
OP6
D0
D2
D4
D6
INTRN
6
5
4
3
2
1
44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
CE•
RESET
X2
X1/CLK•
RXDA
NC
TXDA
OP0
A4
IPO
A3
A4
IP0
R/WN
7
8
39 CS
38
•
A3
IP0
WR•
7
8
9
E
i
E
i
IPO
WRN
RDN
RxDB
TxDB
OP1
OP3
OP5
OP7
D1
RESET•
X2
RESET
X2
R/W•
DTACK•
RxDB
TxDB
OP1
OP3
OP5
OP7
D1
D3
D5
D7
GND
37
36
35
34
33
32
31
30
29
9
9
6
8
C
6
8
1
9
8
8
C
6
8
1
X1/CLK
RxDA
TxDA
OP0
OP2
OP4
OP6
D0
D2
D4
D6
INTR•
DTACK
RXDB 11
10
•
X1/CLK
RXDA
NC
TXDA
OP0
OP2
OP4
OP6
•
RD• 10
RXDB 11
NC 12
TXDB 13
OP1 14
OP3 15
OP5 16
OP7 17
10
11
12
13
14
15
16
17
18
19
20
10
11
12
13
14
15
16
17
18
19
20
Ei88C681
12
13
14
15
16
17
NC
TXDB
OP1
OP3
OP5
Ei68C681
OP2
OP4
OP6
OP7
18 19 20 21 22 23 24 25 26 27 28
D3
D5
D7
GND
40-PIN DIP
40-PIN DIP
44-PIN PLCC
44-PIN PLCC
13
For additional information, contact IMP, Inc. at 408.432.9100 or visit www.impweb.com
IMP, Inc. acquired Epic products on January 26, 2001. (see press release at http://www.impweb.com/PRESS/PR012601.htm)
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