Datasheet > EBE21RD4AGFA

EBE21RD4AGFA

更新时间： 2022-11-25 10:59:10

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
23页	183K
描述
2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 2 Ranks)

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数据手册

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EBE21RD4AGFA 数据手册

EBE21RD4AGFA

Pin Description

Pin name

Function

Address input

Row address

Column address

A0 to A13

A0 to A9, A11

A10 (AP)

Auto precharge

BA0, BA1

Bank select address

Data input/output

DQ0 to DQ63

CB0 to CB7

Check bit (Data input/output)

Row address strobe command

Column address strobe command

Write enable

/RAS

/CAS

/WE

/CS0, /CS1

Chip select

CKE0, CKE1

Clock enable

CK0

Clock input

/CK0

Differential clock input

DQS0 to DQS17, /DQS0 to /DQS17

Input and output data strobe

Clock input for serial PD

Data input/output for serial PD

Serial address input

SCL

SDA

SA0 to SA2

VDD

Power for internal circuit

Power for serial EEPROM

Input reference voltage

Ground

VDDSPD

VREF

VSS

ODT0, ODT1

/RESET

Par_In*²

Err_Out*²

ODT control

Reset pin (forces register and PLL inputs low) *¹

Parity bit for the address and control bus

Parity error found on the address and control bus

No connection

Notes: 1. Reset pin is connected to both OE of PLL and reset to register.

2. NC/Err_Out (Pin No. 55) and NC/Par_In (Pin No. 68) are for optional function to check address and

command parity.

Data Sheet E0794E20 (Ver. 2.0)

1 2 345 6 7...23

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