Datasheet > E-STLC7550TQF7

E-STLC7550TQF7

更新时间： 2024-01-29 02:35:26

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		电信电信集成电路
页数	文件大小	规格书
24页	259K
描述
56kbps DATA, MODEM-SUPPORT CIRCUIT, PQFP48, 7 X 7 MM, 1.4 MM HEIGHT, LEAD FREE, TQFP-48

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E-STLC7550TQF7 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFP
包装说明：	LFQFP, QFP48,.35SQ,20	针数：	48
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.72	数据速率：	56 Mbps
JESD-30 代码：	S-PQFP-G48	JESD-609代码：	e3/e4
长度：	7 mm	湿度敏感等级：	1
功能数量：	1	端子数量：	48
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFQFP
封装等效代码：	QFP48,.35SQ,20	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	260
电源：	3 V	认证状态：	Not Qualified
座面最大高度：	1.6 mm	子类别：	Modems
标称供电电压：	3 V	表面贴装：	YES
技术：	CMOS	电信集成电路类型：	MODEM-SUPPORT CIRCUIT
温度等级：	COMMERCIAL	端子面层：	TIN/NICKEL PALLADIUM GOLD
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	7 mm	Base Number Matches：	1

E-STLC7550TQF7 数据手册

STLC7550

Pins description & Block diagram

Digital Ground (DGND)

This pin is the ground for DAC and ADC internal digital circuitry.

1.1.2

Host interface (10 pins)

Data In (DIN)

In Data Mode, the data word is the input of the DAC channel. In software, the data word is

followed by the control register word.

Data Out (DOUT)

In Data Mode, the data word is the ADC conversion result. In software, the data word is

followed by the register read.

Frame Synchronization (FS)

In master mode, the frame synchronization signal is used to indicate that the device is ready

to send and receive data. The data transfer begins on the falling edge of the frame-sync

signal. The framesync is generated internally and goes low on the rising edge of SCLK in

master mode. In slave mode the frame is generated externally.

Serial Bit Clock (SCLK)

SCLK clocks the digital data into DIN and out of DOUT during the frame synchronization

interval. The Serial bit clock is generated internally.

Reset Function (RESET)

The reset function is to initialize the internal counters and control register. A minimum low

pulse of 100ns is required to reset the chip. This reset function initiates the serial data

communications. The reset function will initialize all the registers to their default value and

will put the device in a pre-programmed state. After a low-going pulse on RESET, the device

registers will be initialized to provide an over-sampling ratio equal to 160, the serial interface

will be in data mode, the DAC attenuation will be set to infinite, the ADC gain will be set to

0dB, the Differential input mode on the ADC converter will be selected, and the multiplexor

will be set on the main inputs IN+ and IN-. After a reset condition, the first frame

synchronization corresponds to the primary channel.

Power Down (PWRDWN)

The Power-Down input powers down the entire chip (< 50mW). When PWRDWN Pin is

taken low, the device powers down such that the existing internally programmed state is

maintained. When PWRDWN is driven high, full operation resumes after 1ms. If the

PWRDWN input is not used, it should be tied to V

Hardware Control (HC0, HC1)

These two pins are used for Hardware/Software Control of the device. The data on HC0 and

HC1 will be latched on to the device on the rising edge of the Frame Synchronization Pulse.

If these two pins are low, Software Control Mode is selected. When in Software Control

Mode, the LSB of the 16-bit word will select the Data Mode (LSB = 0) or the Control Mode

(LSB = 1). Other combinations of HC0/HC1 are for Hardware Control. These inputs should

be tied low if not used.

Rev 9

5/24

1 2 3 456 7 8...24

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