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DS2404B PDF预览

DS2404B

更新时间: 2024-01-11 07:17:47
品牌 Logo 应用领域
达拉斯 - DALLAS 计时器或实时时钟微控制器和处理器外围集成电路光电二极管
页数 文件大小 规格书
28页 664K
描述
EconoRAM Time Chip

DS2404B 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:0.300 INCH, SOIC-16针数:16
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.8
其他特性:1 HZ FIXED O/P; 64-BIT LASERED ROM; TIMEKEEPING CURRENT = 350NA最大时钟频率:0.032 MHz
信息访问方法:SERIAL, 3-WIREJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:10.3 mm
湿度敏感等级:1端子数量:16
计时器数量:最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):240
认证状态:Not Qualified座面最大高度:2.65 mm
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
uPs/uCs/外围集成电路类型:TIMER, REAL TIME CLOCKBase Number Matches:1

DS2404B 数据手册

 浏览型号DS2404B的Datasheet PDF文件第1页浏览型号DS2404B的Datasheet PDF文件第2页浏览型号DS2404B的Datasheet PDF文件第4页浏览型号DS2404B的Datasheet PDF文件第5页浏览型号DS2404B的Datasheet PDF文件第6页浏览型号DS2404B的Datasheet PDF文件第7页 
DS2404  
The “Power Control” section provides for two basic power configurations, battery operate mode and VCC  
operate mode. The battery operate mode utilizes one supply connected to VBATO . The VCC operate mode  
may utilize two supplies; the primary supply connects to VCC and a backup supply connects to VBATB  
.
DS2404 BLOCK DIAGRAM Figure 1  
COMMUNICATION PORTS  
Two communication ports are provided, a 1-Wire and a 3-wire port. The advantages of using the 1-Wire  
port are as follows: 1) provides access to the 64-bit lasered ROM, 2) consists of a single communication  
signal (I/O), and 3) multiple devices may be connected to the 1-Wire bus. The 1-Wire bus has a  
maximum data rate of 16.3k bits/second and requires one 5kW external pullup.  
The 3-wire port consists of three signals, RST , CLK, and DQ. RST is an enable input, DQ is bidirectional  
serial data, and the CLK input is used to clock in or out the serial data. The advantages of using the 3-  
wire port are 1) high data transfer rate (2 MHz), 2) simple timing, and 3) no external pullup required.  
Port selection is accomplished on a first-come, first-serve basis. Whichever port comes out of reset first  
will obtain control. For the 3-wire port, this is done by bringing RST high. For the 1-Wire port, this is  
done on the first falling edge of I/O after the reset and presence pulses. (See “1-Wire Signaling” section.)  
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020998  

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