Datasheet > DS1485TM

DS1485TM

更新时间： 2024-01-13 03:58:04

品牌	Logo	应用领域
其他 - ETC		驱动器接口集成电路光电二极管
页数	文件大小	规格书
17页	251K
描述
Transceiver

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DS1485TM 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	DIP, DIP8,.3	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.91	差分输出：	YES
驱动器位数：	1	高电平输入电流最大值：	0.000001 A
输入特性：	DIFFERENTIAL SCHMITT TRIGGER	接口集成电路类型：	LINE TRANSCEIVER
接口标准：	EIA-422; EIA-485	JESD-30 代码：	R-PDIP-T8
JESD-609代码：	e0	长度：	9.817 mm
功能数量：	1	端子数量：	8
最高工作温度：	85 °C	最低工作温度：	-40 °C
最小输出摆幅：	1.5 V	最大输出低电流：	0.004 A
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装等效代码：	DIP8,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V	认证状态：	Not Qualified
最大接收延迟：	12 ns	接收器位数：	1
座面最大高度：	5.08 mm	子类别：	Line Driver or Receivers
最大压摆率：	5 mA	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	NO	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
最大传输延迟：	10 ns	宽度：	7.62 mm
Base Number Matches：	1

DS1485TM 数据手册

DS1486/DS1486P

DESCRIPTION

The DS1486 is a nonvolatile Static RAM with a full function Real-time clock (RTC), alarm, watchdog

timer, and interval timer which are all accessible in a bytewide format. The DS1486 contains a lithium

energy source and a quartz crystal which eliminate the need for any external circuitry. Data contained

within 128K by 8-bit memory and the timekeeping registers can be read or written in the same manner as

bytewide static RAM. The timekeeping registers are located in the first 14 bytes of memory space. Data

is maintained in the RAMified Timekeeper by intelligent control circuitry which detects the status of V_CC

and write-protects memory when V_CCis out of tolerance. The lithium energy source can maintain data and

real time for over 10 years in the absence of V_CC. Timekeeper information includes hundredths of

seconds, seconds, minutes, hours, day, date, month, and year. The date at the end of the month is

automatically adjusted for months with less than 31 days, including correction for leap year. The

RAMified Timekeeper operates in either 24-hour or 12-hour format with an AM/PM indicator. The

watchdog timer provides alarm interrupts and interval timing between 0.01 seconds and 99.99 seconds.

The real time alarm provides for preset times of up to one week. Interrupts for both watchdog and RTC

will operate when system is powered down. Either can provide system “wake-up” signals.

PACKAGES

The DS1486 is available in two packages: 32-pin DIP module and 34-pin PowerCap module. The 32-pin

DIP style module integrates the crystal, lithium energy source, and silicon all in one package. The 32-pin

PowerCap Module Board is designed with contacts for connection to a separate PowerCap

(DS90934PCX) that contains the crystal and battery. The design allows the PowerCap to be mounted on

top of the DS1486P after the completion of the surface mount process. Mounting the PowerCap after the

surface mount process prevents damage to the crystal and battery due to high temperatures required for

solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and

PowerCap are ordered separately and shipped in separate containers. The part number for the PowerCap

is DS9034PCX.

OPERATION - READ REGISTERS

The DS1486 executes a read cycle whenever WE (Write Enable) is inactive (High), CE (Chip Enable)

and OE (Output Enable) are active (Low). The unique address specified by the address inputs (A0-A16)

defines which of the registers is to be accessed. Valid data will be available to the eight data output

drivers within t_ACC(Access Time) after the last address input signal is stable, providing that CE and OE

access times are also satisfied. If OE and CE access times are not satisfied, then data access must be

measured from the latter occurring signal (CE or OE ) and the limiting parameter is either t_COfor CE or

t_OEfor OE rather than address access.

OPERATION - WRITE REGISTERS

The DS1486 is in the write mode whenever the WE (Write Enable) and CE (Chip Enable) signals are in

the active (Low) state after the address inputs are stable. The latter occurring falling edge of CE or WE

will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE

or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state

for a minimum recovery state (t_WR) before another cycle can be initiated. Data must be valid on the data

bus with sufficient Data Set-Up (t_DS) and Data Hold Time (t_DH) with respect to the earlier rising edge of

CE or WE . The OE control signal should be kept inactive (High) during write cycles to avoid bus

contention. However, if the output bus has been enabled (CE and OE active), then WE will disable the

outputs in t_ODWfrom its falling edge.

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与DS1485TM相关器件

型号	品牌	描述	获取价格	数据表
DS1485TN	NSC	IC LINE TRANSCEIVER, PDIP8, 0.300 INCH, PLASTIC, DIP-8, Line Driver or Receiver	获取价格
DS1486	DALLAS	RAMified Watchdog Timekeeper	获取价格
DS1486-120	DALLAS	RAMified Watchdog Timekeeper	获取价格
DS1486-150	DALLAS	RAMified Watchdog Timekeeper	获取价格
DS1486P	DALLAS	RAMified Watchdog Timekeeper	获取价格
DS1486P-120	MAXIM	Real Time Clock, Non-Volatile, 1 Timer(s), CMOS, POWERCAP MODULE-34	获取价格

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