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DS1482S/T PDF预览

DS1482S/T

更新时间: 2024-02-14 19:59:30
品牌 Logo 应用领域
达拉斯 - DALLAS 驱动器转换器电平转换器传感器
页数 文件大小 规格书
7页 216K
描述
1-Wire Level Shifter and Line Driver with Load Sensor

DS1482S/T 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP,
针数:16Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.62Is Samacsys:N
差分输出:NO驱动器位数:1
输入特性:STANDARD接口集成电路类型:LINE DRIVER
接口标准:GENERAL PURPOSEJESD-30 代码:R-PDSO-G16
JESD-609代码:e3长度:9.9 mm
湿度敏感等级:1功能数量:1
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
认证状态:Not Qualified最大接收延迟:
接收器位数:1座面最大高度:1.75 mm
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V电源电压1-最大:3.6 V
电源电压1-分钟:3 V电源电压1-Nom:3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm
Base Number Matches:1

DS1482S/T 数据手册

 浏览型号DS1482S/T的Datasheet PDF文件第1页浏览型号DS1482S/T的Datasheet PDF文件第2页浏览型号DS1482S/T的Datasheet PDF文件第3页浏览型号DS1482S/T的Datasheet PDF文件第4页浏览型号DS1482S/T的Datasheet PDF文件第5页浏览型号DS1482S/T的Datasheet PDF文件第6页 
DS1482  
PARAMETER  
OUTPUT PIN RXD  
Output-Low Voltage  
Output-High Voltage  
Output Rise Time  
(50pF Load)  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX UNITS  
VOL  
VOH  
100µA load  
-100µA load  
0.4  
V
V
VCCQ - 0.5V  
tR  
0.1 x VCCQ to 0.9 x VCCQ  
50  
50  
ns  
ns  
ns  
Output Fall Time  
(50pF Load)  
tF  
0.9 x VCCQ to 0.1 x VCCQ  
See Figure 6 (Note 2)  
Delay I/O to RXD  
(50pF Load)  
tIR  
100  
OUTPUT PIN PCTLZ  
Output-Low Voltage  
Output-High Voltage  
Output Rise Time  
(50pF Load)  
VOL  
VOH  
100µA load  
-100µA load  
0.4  
V
V
VCC - 0.5V  
tR  
0.1 x VCC to 0.9 x VCC  
0.9 x VCC to 0.1 x VCC  
See Figure 7 (Note 4)  
50  
50  
ns  
ns  
ns  
Output Fall Time  
(50pF Load)  
tF  
Delay SPU to PCTLZ  
(50pF Load)  
tSP  
100  
OUTPUT PIN DONE  
Output-Low Voltage  
Output-High Voltage  
Output Rise Time  
(50pF Load)  
VOL  
VOH  
100µA load  
-100µA load  
0.4  
V
V
VCCQ - 0.5V  
tR  
0.1 x VCCQ to 0.9 x VCCQ  
0.9 x VCCQ to 0.1 x VCCQ  
START at V
CCQ
(Note 5)  
See Figure 8  
50  
50  
ns  
ns  
µs  
ns  
Output Fall Time  
(50pF Load)  
tF  
Delay I/O to DONE  
(50pF Load)  
Delay START to  
DONE (50pF Load)  
tCF  
tSD  
128  
500  
100  
The input pins have a weak pulldown.  
Note 1:  
Note 2:  
For OD read- or write-1 time slots, TXD should be pulsed high for 1.28µs. The window for  
sampling RXD begins 1.8µs after TXD has turned high and ends 2.05µs after TXD has turned  
high. RXD must be sampled inside this window. Correct sampling can be achieved with the  
particular recommended microcontroller Hitachi SH7622 if the peripheral module operating  
frequency Pis higher or equal to 22MHz.  
Measured either with VCC on the pin and TXD low or with 0V on the pin and TXD high. This  
parameter is guaranteed by design, and is not production tested.  
Note 3:  
The PCTLZ signal is gated by TXD. The PCTLZ output is only low if TXD is low.  
Characteristic of the glitch-eating filter on the output of the load-sensing comparator, i.e., an  
event where the downstream 1-Wire slave device is sinking high current, ceases sinking the  
current for less than this amount of time, and resumes sinking the current does not generate  
high level on DONE; DONE goes high this amount of time after the downstream 1-Wire slave  
device has ceased sinking high current.  
Note 4:  
Note 5:  
7 of 7  

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