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DS1086LU+ PDF预览

DS1086LU+

更新时间: 2024-02-14 05:20:42
品牌 Logo 应用领域
美信 - MAXIM 模拟IC信号电路光电二极管
页数 文件大小 规格书
17页 233K
描述
3.3V Spread-Spectrum EconOscillator

DS1086LU+ 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP,针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:5.27Is Samacsys:N
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:4.88 mm湿度敏感等级:1
端子数量:8最高工作温度:70 °C
最低工作温度:最大输出时钟频率:133 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.75 mm最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9116 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

DS1086LU+ 数据手册

 浏览型号DS1086LU+的Datasheet PDF文件第2页浏览型号DS1086LU+的Datasheet PDF文件第3页浏览型号DS1086LU+的Datasheet PDF文件第4页浏览型号DS1086LU+的Datasheet PDF文件第6页浏览型号DS1086LU+的Datasheet PDF文件第7页浏览型号DS1086LU+的Datasheet PDF文件第8页 
3.3V Spread-Spectrum EconOscillator  
DS1086L  
AC ELECTRICAL CHARACTERISTICS—2-WIRE INTERFACE (continued)  
(V  
= 2.7V to 3.6V, T = -40°C to +85°C.)  
A
CC  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
0.6  
TYP  
MAX  
UNITS  
Fast mode  
Setup Time for STOP  
t
µs  
SU:STO  
Standard mode  
4.0  
Capacitive Load for Each Bus  
Line  
C
(Note 16)  
400  
10  
pF  
B
EEPROM Write Cycle Time  
Input Capacitance  
t
ms  
pF  
WR  
C
5
I
NONVOLATILE MEMORY CHARACTERISTICS  
(V  
= 2.7V to 3.6V)  
CC  
PARAMETER  
EEPROM Writes  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
+70°C  
10,000  
Note 1:  
Note 2:  
All voltages are referenced to ground.  
DAC and OFFSET register settings must be configured to maintain the master oscillator frequency within this range.  
Correct operation of the device is not guaranteed if these limits are exceeded.  
Note 3:  
Note 4:  
This is the absolute accuracy of the master oscillator frequency at the default settings.  
This is the change that is observed in master oscillator frequency with changes in voltage from nominal voltage at  
T
A
= +25°C.  
Note 5:  
This is the percentage frequency change from the +25°C frequency due to temperature at V = 3.3V. The maximum temper-  
CC  
ature change varies with the master oscillator frequency setting. The minimum occurs at the default master oscillator frequen-  
cy (f ). The maximum occurs at the extremes of the master oscillator frequency range (33.3MHz or 66.6MHz).  
default  
Note 6:  
Note 7:  
The dither deviation of the master oscillator frequency is unidirectional and lower than the undithered frequency.  
The integral nonlinearity of the frequency is a measure of the deviation from a straight line drawn between the two end-  
points (f  
to f  
) of the range. The error is in percentage of the span.  
osc(MIN)  
osc(MAX)  
Note 8:  
Note 9:  
This is true when the prescaler = 1.  
Frequency settles faster for small changes in value. During a change, the frequency transitions smoothly from the original  
value to the new value.  
Note 10: This indicates the time elapsed between power-up and the output becoming active. An on-chip delay is intentionally  
introduced to allow the oscillator to stabilize. t is equivalent to approximately 512 master clock cycles and therefore  
stab  
depends on the programmed clock frequency.  
Note 11: Output voltage swings can be impaired at high frequencies combined with high output loading.  
Note 12: A fast-mode device can be used in a standard-mode system, but the requirement t > 250ns must then be met.  
SU:DAT  
This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does  
stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line at least t  
1000ns + 250ns = 1250ns before the SCL line is released.  
+ t  
=
R MAX  
SU:DAT  
Note 13: After this period, the first clock pulse is generated.  
Note 14: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the V  
of the SCL  
IH MIN  
signal) to bridge the undefined region of the falling edge of SCL.  
Note 15: The maximum t  
need only be met if the device does not stretch the LOW period (t  
) of the SCL signal.  
HD:DAT  
LOW  
Note 16: C —total capacitance of one bus line, timing referenced to 0.9 x V  
and 0.1 x V  
.
B
CC  
CC  
Note 17: Typical frequency shift due to aging is 0.5%. Aging stressing includes Level 1 moisture reflow preconditioning (24hr  
+125°C bake, 168hr 85°C/85%RH moisture soak, and three solder reflow passes +240 +0/-5°C peak) followed by 1000hr  
max V  
biased 125°C HTOL, 1000 temperature cycles at -55°C to +125°C, 96hr 130°C/85%RH/3.6V HAST and 168hr  
CC  
121°C/2 ATM Steam/Unbiased Autoclave.  
t is the time required after exiting power-down to the beginning of output oscillations. In addition, a delay of t  
stab  
Note 18:  
DACstab  
is required before the frequency will be within its specified tolerance.  
_______________________________________________________________________________________  
5

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