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DP83620SQ/NOPB PDF预览

DP83620SQ/NOPB

更新时间: 2024-01-07 09:27:46
品牌 Logo 应用领域
德州仪器 - TI 网络接口电信集成电路电信电路以太网局域网(LAN)标准以太网:16GBASE-T
页数 文件大小 规格书
105页 1311K
描述
DP83620 Industrial Temperature Single Port 10/100 Mbps Ethernet Physical Layer

DP83620SQ/NOPB 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:HVQCCN, LCC48,.27SQ,20
Reach Compliance Code:compliantECCN代码:5A991.B.1
HTS代码:8542.39.00.01Factory Lead Time:8 weeks
风险等级:1.27Is Samacsys:N
数据速率:100000 MbpsJESD-30 代码:S-PQCC-N48
JESD-609代码:e3长度:7 mm
湿度敏感等级:2功能数量:1
端子数量:48收发器数量:1
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装等效代码:LCC48,.27SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:2.5/3.3,3.3 V认证状态:Not Qualified
座面最大高度:0.8 mm子类别:Network Interfaces
标称供电电压:3.3 V表面贴装:YES
技术:CMOS电信集成电路类型:ETHERNET TRANSCEIVER
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7 mmBase Number Matches:1

DP83620SQ/NOPB 数据手册

 浏览型号DP83620SQ/NOPB的Datasheet PDF文件第1页浏览型号DP83620SQ/NOPB的Datasheet PDF文件第3页浏览型号DP83620SQ/NOPB的Datasheet PDF文件第4页浏览型号DP83620SQ/NOPB的Datasheet PDF文件第5页浏览型号DP83620SQ/NOPB的Datasheet PDF文件第6页浏览型号DP83620SQ/NOPB的Datasheet PDF文件第7页 
DP83620  
SNLS339C JANUARY 2011REVISED APRIL 2013  
www.ti.com  
4.24 AC Specifications — Auto-Negotiation Fast Link  
1
Introduction .............................................. 1  
1.1 Features ............................................. 1  
1.2 Applications .......................................... 1  
1.3 Description ........................................... 1  
Device Information ...................................... 4  
2.1 System Diagram ..................................... 4  
2.2 Block Diagram ....................................... 4  
Pin Descriptions ......................................... 5  
3.1 Pin Layout ........................................... 6  
3.2 PACKAGE PIN ASSIGNMENTS .................... 7  
3.3 SERIAL MANAGEMENT INTERFACE .............. 8  
3.4 MAC DATA INTERFACE ............................ 8  
3.5 CLOCK INTERFACE ................................ 9  
3.6 LED INTERFACE .................................... 9  
3.7 JTAG INTERFACE ................................. 10  
3.8 RESET AND POWER DOWN ...................... 10  
3.9 STRAP OPTIONS .................................. 10  
3.10 10 Mb/s AND 100 Mb/s PMD INTERFACE ........ 12  
3.11 RESERVED PINS .................................. 12  
3.12 POWER SUPPLY PINS ............................ 12  
Electrical Specifications ............................. 13  
4.1 Absolute Maximum Ratings ........................ 13  
4.2 Recommended Operating Conditions .............. 13  
4.3 AC and DC Specifications .......................... 13  
4.4 DC Specifications .................................. 14  
4.5 AC Specifications — Power Up Timing ............ 15  
4.6 AC Specifications — Reset Timing ................. 16  
Pulse (FLP) Timing ................................. 23  
4.25 AC Specifications — 100BASE-TX Signal Detect  
Timing .............................................. 24  
4.26 AC Specifications — 100 Mb/s Internal Loopback  
Timing .............................................. 24  
4.27 AC Specifications — 10 Mb/s Internal Loopback  
Timing .............................................. 25  
4.28 AC Specifications — RMII Transmit Timing (Slave  
Mode) ............................................... 25  
4.29 AC Specifications — Transmit Timing (Master  
Mode) ............................................... 26  
4.30 AC Specifications — RMII Receive Timing (Slave  
Mode) ............................................... 27  
4.31 AC Specifications — RMII Receive Timing (Master  
Mode) ............................................... 28  
4.32 AC Specifications — RX_CLK Timing (RMII Master  
Mode) ............................................... 28  
4.33 AC Specifications — CLK_OUT Timing (RMII Slave  
Mode) ............................................... 29  
4.34 AC Specifications — Single Clock MII (SCMII)  
Transmit Timing .................................... 29  
4.35 AC Specifications — Single Clock MII (SCMII)  
Receive Timing ..................................... 30  
4.36 AC Specifications — 100 Mb/s X1 to TX_CLK  
Timing .............................................. 30  
2
3
4
5
Configuration ........................................... 31  
5.1 MEDIA CONFIGURATION ......................... 31  
5.2 AUTO-NEGOTIATION .............................. 31  
5.3 AUTO-MDIX ........................................ 34  
5.4  
AUTO-CROSSOVER IN FORCED MODE ......... 34  
4.7  
4.8  
4.9  
AC Specifications — MII Serial Management Timing  
...................................................... 17  
AC Specifications — 100 Mb/s MII Transmit Timing  
...................................................... 17  
5.5 PHY ADDRESS .................................... 34  
5.6 LED INTERFACE ................................... 35  
5.7 HALF DUPLEX vs. FULL DUPLEX ................ 37  
5.8 INTERNAL LOOPBACK ............................ 38  
5.9 POWER DOWN/INTERRUPT ...................... 38  
5.10 ENERGY DETECT MODE ......................... 38  
5.11 LINK DIAGNOSTIC CAPABILITIES ................ 39  
5.12 BIST ................................................ 43  
MAC Interface .......................................... 44  
6.1 MII INTERFACE .................................... 44  
6.2 REDUCED MII INTERFACE ....................... 45  
6.3 SINGLE CLOCK MII MODE ........................ 46  
AC Specifications — 100 Mb/s MII Receive Timing 17  
4.10 AC Specifications — 100BASE-TX and 100BASE-  
FX MII Transmit Packet Latency Timing ........... 18  
4.11 AC Specifications — 100BASE-TX and 100BASE-  
FX MII Transmit Packet Deassertion Timing ....... 18  
4.12 AC Specifications — 100BASE-TX Transmit Timing  
(tR/F & Jitter) ........................................ 19  
4.13 AC Specifications — 100BASE-TX and 100BASE-  
FX MII Receive Packet Latency Timing ............ 19  
4.14 AC Specifications — 100BASE-TX and 100BASE-  
FX MII Receive Packet Deassertion Timing ....... 20  
6
6.4  
IEEE 802.3u MII SERIAL MANAGEMENT  
4.15 AC Specifications — 10 Mb/s MII Transmit Timing 20  
INTERFACE ........................................ 47  
4.16 AC Specifications — 10 Mb/s MII Receive Timing . 20  
4.17 AC Specifications — 10BASE-T MII Transmit  
Timing (Start of Packet) ............................ 21  
4.18 AC Specifications — 10BASE-T MII Transmit  
6.5 PHY CONTROL FRAMES ......................... 48  
6.6 PHY STATUS FRAMES ............................ 49  
Architecture ............................................. 50  
7.1 100BASE-TX TRANSMITTER ...................... 50  
7.2 100BASE-TX RECEIVER .......................... 53  
7.3 100BASE-FX OPERATION ......................... 57  
7.4 10BASE-T TRANSCEIVER MODULE .............. 58  
Reset Operation ........................................ 61  
8.1 HARDWARE RESET ............................... 61  
8.2 FULL SOFTWARE RESET ......................... 61  
8.3 SOFT RESET ...................................... 61  
Design Guidelines ..................................... 62  
7
Timing (End of Packet) ............................. 21  
4.19 AC Specifications — 10BASE-T MII Receive Timing  
(Start of Packet) .................................... 22  
4.20 AC Specifications — 10BASE-T MII Receive Timing  
(End of Packet) ..................................... 22  
8
9
4.21 AC Specifications — 10 Mb/s Heartbeat Timing ... 22  
4.22 AC Specifications — 10 Mb/s Jabber Timing ...... 23  
4.23 AC Specifications — 10BASE-T Normal Link Pulse  
Timing .............................................. 23  
2
Contents  
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