DLP3000
www.ti.com
DLPS022 –JANUARY 2012
Mobile DDR RAM
Red PWN,
Green PWM,
Blue PWM
PCLK
DVI
Receiver
(TVP5151)
LED
Drivers
HSYNC,VSYNC
24-Bit RGB Data
LEDs
Digital Video
LED Strobes
Illumination
Optics
2
I2C
LED
Sensor
DLPC300
Control
2
I2C
Control
Processor
(MSP430)
DMD Control
DMD Data
DLP3000
OSC
DMD™
Voltage
Supplies
SPI
FLASH
Figure 2. Typical Application
Electrically, the DLP3000 consists of a two-dimensional array of 1-bit CMOS memory cells, organized in a grid of
608 memory cell columns by 684 memory cell rows. The CMOS memory array is addressed on
column-by-column basis, over a 15-bit double data rate (DDR) bus. Addressing is handled via a serial control
bus. The specific CMOS memory access protocol is handled by the DLPC300 digital controller.
Optically, the DLP3000 consists of 415,872 highly reflective, digitally switchable, micrometer-sized mirrors
(micromirrors) organized in a two-dimensional array. The micromirror array consists of 608 micromirror columns
by 684 micromirror rows in diamond pixel configuration (Figure 3). Due to the diamond pixel configuration, the
columns of each odd row are offset by half a pixel from the columns of the even row.
Each aluminum micromirror is approximately 7.6 microns in size (see Micromirror Pitch in Figure 3), and is
switchable between two discrete angular positions: –12° and +12°. The angular positions are measured relative
to a 0° flat reference when the mirrors are parked in their inactive state, parallel to the array plane (see Figure 4).
The tilt direction is perpendicular to the hinge-axis. The on-state landed position is directed toward the left side of
the package (see DLP3000 Active Mirror Array, Micromirror Pitch, and Micromirror Hinge-Axis Orientation in
Figure 3).
Each individual micromirror is positioned over a corresponding CMOS memory cell. The angular position of a
specific micromirror is determined by the binary state (logic 0 or 1) of the corresponding CMOS memory cell
contents, after the mirror clocking pulse is applied. The angular position (–12° or +12°) of the individual
micromirrors changes synchronously with a micromirror clocking pulse, rather than being coincident with the
CMOS memory cell data update. Therefore, writing a logic 1 into a memory cell followed by a mirror clocking
pulse results in the corresponding micromirror switching to a +12° position. Writing a logic 0 into a memory cell
followed by a mirror clocking pulse results in the corresponding micromirror switching to a –12° position.
Copyright © 2012, Texas Instruments Incorporated
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