DLO32F-3.5MD4

更新时间： 2024-01-16 06:55:30

品牌	Logo	应用领域
DATADELAY		振荡器延迟线
页数	文件大小	规格书
4页	46K
描述
TTL-INTERFACED, GATED DELAY LINE OSCILLATOR

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数据手册

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DLO32F-3.5MD4 数据手册

DLO32F

DELAY LINE AUTOMATED TESTING

TEST CONDITIONS

INPUT:

OUTPUT:

Ambient Temperature: 25^oC ± 3^oC

Supply Voltage (Vcc): 5.0V ± 0.1V

Load:

C_load

1 FAST-TTL Gate

5pf ± 10%

Input Pulse:

High = 3.0V ± 0.1V

Threshold: 1.5V (Rising & Falling)

Low = 0.0V ± 0.1V

Source Impedance:

Rise/Fall Time:

50W Max.

3.0 ns Max. (measured

between 0.6V and 2.4V )

PW_IN= 10 x Clock Period

PER_IN= 20 x Clock Period

Pulse Width Low:

Period:

NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.

FREQUENCY

COUNTER

OUT

PULSE

GENERATOR

DEVICE UNDER

TEST (DUT)

OSCILLOSCOPE

TRIG

Test Setup

PER_IN

PW_IN

T_FALL

T_RISE

2.4V

1.5V

0.6V

2.4V

1.5V

0.6V

INPUT

SIGNAL

V_IH

V_IL

T_EO

OUTPUT

SIGNAL

V_OH

1.5V

V_OL

Timing Diagram For Testing

Doc #98002

3/17/98

DATA DELAY DEVICES, INC.

Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

1 2 34

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