DLO31F-3.5MD4

更新时间： 2024-01-25 02:54:42

品牌	Logo	应用领域
DATADELAY		振荡器延迟线
页数	文件大小	规格书
4页	46K
描述
TTL-INTERFACED, GATED DELAY LINE OSCILLATOR (SERIES DLO31F)

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DLO31F-3.5MD4 数据手册

DLO31F

APPLICATION NOTES

THERMAL STABILITY

POWER SUPPLY BYPASSING

The delay line used internally to develop the clock

signals in the DLO31F has a thermal coefficient

of 100ppm/C. For low frequency units, this is also

the thermal coefficient of the output frequency.

For higher frequency units, however, other

internal effects must be considered, and the

actual thermal coefficient may be somewhat

higher.

The DLO31F relies on a stable power supply to

produce a repeatable frequency within the stated

tolerances. A 0.1uf capacitor from VCC to GND,

located as close as possible to the VCC pin, is

recommended. A wide VCC trace and a clean

ground plane should be used.

DEVICE SPECIFICATIONS

TABLE 1: ABSOLUTE MAXIMUM RATINGS

PARAMETER

DC Supply Voltage

Input Pin Voltage

Storage Temperature

Lead Temperature

SYMBOL

V_CC

V_IN

T_STRG

T_LEAD

MIN

-0.3

-55

MAX

7.0

V_DD+0.3

150

UNITS NOTES

300

10 sec

TABLE 2: DC ELECTRICAL CHARACTERISTICS

(0C to 70C, 4.75V to 5.25V)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

High Level Output Voltage

V_OH

2.5

3.4

V_CC= MIN, I_OH= MAX

V_IH= MIN, V_IL= MAX

V_CC= MIN, I_OL= MAX

V_IH= MIN, V_IL= MAX

Low Level Output Voltage

V_OL

0.35

0.5

High Level Output Current

Low Level Output Current

High Level Input Voltage

Low Level Input Voltage

Input Clamp Voltage

Input Current at Maximum

Input Voltage

High Level Input Current

Low Level Input Current

Short-circuit Output Current

Output High Fan-out

I_OH

I_OL

V_IH

V_IL

V_IK

I_IHH

-1.0

20.0

2.0

-60

0.8

-1.2

0.1

V_CC= MIN, I_I= I_IK

V_CC= MAX, V_I= 7.0V

I_IH

I_IL

I_OS

-0.6

-150

V_CC= MAX, V_I= 2.7V

V_CC= MAX, V_I= 0.5V

V_CC= MAX

Unit

Load

Output Low Fan-out

12.5

TABLE 3: AC ELECTRICAL CHARACTERISTICS

(0C to 70C, 4.75V to 5.25V)

PARAMETER

SYMBOL MIN TYP MAX

UNITS

Enable to Clock On (Inherent Delay)

Disable to Clock Off

Clock Skew

t_EO

t_DO

t_CS

t_GR

3.5

2.5

5.5

3.5

7.0

4.5

Gate Recovery Time

% of Clock Period

Doc #98001

3/17/98

DATA DELAY DEVICES, INC.

Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

123 4

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