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DG201AEUE PDF预览

DG201AEUE

更新时间: 2024-01-28 15:15:26
品牌 Logo 应用领域
美信 - MAXIM 开关
页数 文件大小 规格书
12页 517K
描述
Quad SPST CMOS Analog Switches

DG201AEUE 技术参数

生命周期:Transferred包装说明:SOIC
Reach Compliance Code:unknown风险等级:5.55
模拟集成电路 - 其他类型:SPSTJESD-30 代码:R-PDSO-G
信道数量:4功能数量:1
最大通态电阻 (Ron):50 Ω封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
认证状态:Not Qualified最大供电电压 (Vsup):44 V
表面贴装:YES最长接通时间:50 ns
端子形式:GULL WING端子位置:DUAL
Base Number Matches:1

DG201AEUE 数据手册

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Quad SPST CMOS Analog Switches  
LOGIC  
INPUT  
LOGIC "0" - SW ON  
3V  
R
L
V = V  
0
S
L
R + R  
DS(ON)  
+15V  
t < 20ns  
f
t < 20ns  
50%  
+
V
SWITCH  
INPUT  
r
SWITCH  
OUTPUT  
0
S
1
D
1
V
V
= +2V  
0
S
SWITCH  
INPUT  
V
S
0
C
35pF  
R
1kΩ  
L
L
V
V
0.9  
0.9  
IN  
0
0
1
LOGIC  
INPUT  
SWITCH  
OUTPUT  
V
0.1  
0
(REPEAT TEST FOR IN , IN , AND IN )  
2
3
4
t
t
ON  
off1  
GND  
V-  
-15V  
0
t
off2  
Figure 1. Switching Time  
Tyꢃꢄcal R  
vs4 Pꢀwer Suꢃꢃlꢄes fꢀr Maxꢄm’s DG20ꢁA, and DG2ꢁꢁ  
DS(VN)  
R
AT ANALVG SIGNAL LE5EL  
DS(VN)  
PVWER SUPPLIES  
-.5  
3ꢀ0  
+.5  
3ꢁ0  
-ꢁ05  
+ꢁ05  
-ꢁ.5  
+ꢁ.5  
±5  
±105  
±1ꢀ5  
16ꢀ  
12ꢀ  
2ꢀ0  
160  
13ꢀ  
1ꢀꢀ  
To provide protection for overvoltages up to 205 above  
the supplies, a 1N±001 or 1N91± type diode should be  
placed in series with the positive and negative supplies  
as shown in Figure 2. The addition of these diodes will  
reduce the analog signal range to 15 below the posi-  
tive supply and 15 above the negative supply.  
Protecting Against Fault  
Conditions  
Fault conditions occur when power supplies are turned  
off when input signals are still present, or when over-  
voltages occur at the inputs during normal operation. In  
either case, source-to-body diodes can be forward  
biased and conduct current from the signal source. If  
this current is required to be kept to low (µA) levels  
then the addition of eꢂternal protection diodes is rec-  
ommended.  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
IN4001  
IN4001  
-15V  
+15V  
DG201A  
DG211  
Pin Configurations (continued)  
TOP VIEW  
D1  
16  
IN1  
15  
IN2  
14  
D2  
13  
S1  
V-  
1
2
3
4
12 S2  
11 V+  
Figure 2. Protection against Fault Conditions  
DG201A  
DG211  
GND  
S4  
N.C.  
10  
9
S3  
5
6
7
8
D4  
IN4  
IN3  
D3  
QFN*  
6
_______________________________________________________________________________________  

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