Datasheet > DAC7541AJP

DAC7541AJP

更新时间： 2024-01-08 00:48:15

品牌	Logo	应用领域
德州仪器 - TI		光电二极管转换器
页数	文件大小	规格书
11页	102K
描述
Low Cost 12-Bit CMOS Four-Quadrant Multiplying D/A Converter 18-PDIP 0 to 70

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DAC7541AJP 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	DIP, DIP18,.3	针数：	18
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	Factory Lead Time：	1 week
风险等级：	5.09	转换器类型：	D/A CONVERTER
输入位码：	BINARY	输入格式：	PARALLEL, WORD
JESD-30 代码：	R-PDIP-T18	JESD-609代码：	e4
长度：	22.48 mm	最大线性误差 (EL)：	0.0244%
位数：	12	功能数量：	1
端子数量：	18	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装等效代码：	DIP18,.3
封装形状：	RECTANGULAR	封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	15 V
认证状态：	Not Qualified	座面最大高度：	5.08 mm
最大稳定时间：	10 µs	标称安定时间 (tstl)：	0.6 µs
子类别：	Other Converters	最大压摆率：	2 mA
标称供电电压：	15 V	表面贴装：	NO
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	7.62 mm
Base Number Matches：	1

DAC7541AJP 数据手册

DISCUSSION

OF SPECIFICATIONS

CIRCUIT DESCRIPTION

The DAC7541A is a 12-bit multiplying D/A converter

consisting of a highly stable thin-film R-2R ladder network

and 12 pairs of current steering switches on a monolithic

chip. Most applications require the addition of a voltage or

current reference and an output operational amplifier.

RELATIVE ACCURACY

This term (also known as linearity) describes the transfer

function of analog output to digital input code. The linearity

error describes the deviation from a straight line between

zero and full scale.

A simplified circuit of the DAC7541A is shown in Figure 1.

The R-2R inverted ladder binarily divides the input currents

that are switched between I_{OUT 1}and I_{OUT 2}bus lines. This

switching allows a constant current to be maintained in each

ladder leg independent of the input code.

DIFFERENTIAL NONLINEARITY

Differential nonlinearity is the deviation from an ideal 1LSB

change in the output, from one adjacent output state to the

next. A differential nonlinearity specification of ±1.0LSB

guarantees monotonicity.

The input resistance at V_REF(Figure 1) is always equal to

R_LDR(R_LDRis the R/2R ladder characteristic resistance and

is equal to value “R”). Since R_INat the V_REFpin is constant,

the reference terminal can be driven by a reference voltage

or a reference current, AC or DC, of positive or negative

polarity.

GAIN ERROR

Gain error is the difference in measure of full-scale output

versus the ideal DAC output. The ideal output for the

DAC7541A is –(4095/4096) X (V_REF). Gain error may be

adjusted to zero using external trims.

V_REF

10kΩ

OUTPUT LEAKAGE CURRENT

The measure of current which appears at Out₁with the DAC

loaded with all zeros, or at Out₂with the DAC loaded with

all ones.

20kΩ

S₁

20kΩ

S₂

20kΩ

S₃

20kΩ

S₁₂

20kΩ

I_{OUT 2}

I_{OUT 1}

R_FB

MULTIPLYING FEEDTHROUGH ERROR

This is the AC error output due to capacitive feedthrough

from V_REFto Out₁with the DAC loaded with all zeros. This

test is performed at 10kHz.

Bit 1

(MSB)

Bit 2

Bit 3

Bit 12

(LSB)

Digital Inputs (DTL-/TTL-/CMOS-compatible)

Switches shown for digital inputs “HIGH”.

OUTPUT CURRENT SETTLING TIME

This is the time required for the output to settle to a tolerance

of ±0.5LSB of final value from a change in code of all zeros

to all ones, or all ones to all zeros.

FIGURE 1. Simplified DAC Circuit.

EQUIVALENT CIRCUIT ANALYSIS

Figures 2 and 3 show the equivalent circuits for all digital

inputs low and high, respectively. The reference current is

switched to I_{OUT 2}when all inputs are low and I_{OUT 1}when

inputs are high. The I_Lcurrent source is the combination of

surface and junction leakages to the substrate; the

1/4096 current source represents the constant one-bit current

drain through the ladder terminal.

PROPAGATION DELAY

This is the measure of the delay of the internal circuitry and

is measured as the time from a digital code change to the

point at which the output reaches 90% of final value.

DIGITAL-TO-ANALOG GLITCH IMPULSE

This is the measure of the area of the glitch energy measured

in nV-seconds. Key contributions to glitch energy are digital

word-bit timing differences, internal circuitry timing differ-

ences, and charge injected from digital logic.

DYNAMIC PERFORMANCE

Output Impedance

The output resistance, as in the case of the output capaci-

tance, is also modulated by the digital input code. The

resistance looking back into the I_{OUT 1}terminal may be

anywhere between 10kΩ (the feedback resistor alone when

all digital inputs are low) and 7.5kΩ (the feedback resistor

in parallel with approximately 30kΩ of the R-2R ladder

network resistance when any single bit logic is high). The

static accuracy and dynamic performance will be affected by

this modulation. The gain and phase stability of the output

MONOTONICITY

Monotonicity assures that the analog output will increase or

stay the same for increasing digital input codes. The

DAC7541A is guaranteed monotonic to 12 bits.

POWER SUPPLY REJECTION

Power supply rejection is the measure of the sensitivity of

the output (full scale) to a change in the power supply

voltage.

DAC7541A

1 2 3 456 7 8...11

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与DAC7541AJP相关器件

型号	品牌	描述	获取价格	数据表
DAC7541AJP-BI	BB	Low Cost 12-Bit CMOS Four-Quadrant Multiplying DIGITAL-TO-ANALOG CONVERTER	获取价格
DAC7541AJPG4	BB	Low Cost 12-Bit CMOS Four-Quadrant Multiplying DIGITAL-TO-ANALOG CONVERTER	获取价格
DAC7541AJPG4	TI	PARALLEL, WORD INPUT LOADING, 0.6us SETTLING TIME, 12-BIT DAC, PDIP18, GREEN, PLASTIC, DIP	获取价格
DAC7541AJU	BB	Low Cost 12-Bit CMOS Four-Quadrant Multiplying DIGITAL-TO-ANALOG CONVERTER	获取价格
DAC7541AJU	TI	Low Cost 12-Bit CMOS Four-Quadrant Multiplying D/A Converter 18-SOP 0 to 70	获取价格
DAC7541AJU-BI	BB	D/A Converter, 1 Func, Parallel, Word Input Loading, 0.6us Settling Time, PDSO18,	获取价格

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