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DAC1243X_SR PDF预览

DAC1243X_SR

更新时间: 2022-01-19 05:40:00
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其他 - ETC /
页数 文件大小 规格书
10页 440K
描述
DAC1243X_SR 10BIT 30MSPS Single Channel DAC DAC1243X_SR|Data Sheet

DAC1243X_SR 数据手册

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DAC1243X-SR  
10BIT 30MSPS Single Channel DAC  
PIN CONFIGURATION  
I/O  
I/O TYPE ABBR.  
NAME  
PDAC  
CLK  
I/O PAD  
piar50_abb  
picc_abb  
PIN DESCRIPTION  
TYPE  
AI : Analog Input  
Just Analog Switch Block power down  
control. When activated(high) all current  
switches are disabled.  
DI : Digital Input  
DI  
AO : Analog Output  
DO : Analog Output  
AB : Analog Bidirectional  
DB : Digital Bidirectional  
DAC master clock. Input data is latched  
DI  
DI  
into the DACs on the rising edge of  
.
CLK  
Control strobe for the DAC auto-load  
detection comparator. When  
transitions  
PRE  
AP : Analog Power  
AG : Analog Ground  
DP : Digital Power  
DG : Digital Ground  
high-to-low, the auto-load detect circuit  
evaluates its analog input. Appropriate  
settling time must be allowed before the  
piar50_abb  
PRE  
comparator output  
is used. When  
(DTOUT)  
not used,  
should be left high.  
PRE  
DI  
DI  
picc_abb  
10-bit straight binary, parallel digital input  
D1[9:0]  
ALLPD  
Power down control for Bandgap and all  
blocks. A high level disables all analog  
switchs and digital blocks plus the bandgap  
piar50_abb  
reference regardless of the states of  
PDAC  
Comparator output for detection of resistive  
load at DAC output. A low at the detect  
output indicates that the output voltage of  
the current selected DAC is above 0.53V  
and therefore that no load is attached.  
DO  
pot8_abb  
DTOUT  
Internal DAC compensation node. Connect  
AB  
AB  
poa_abb_50option  
poa_abb_50option  
CCOMP  
IRSET  
external 0.1uF cap to  
.
VDD25AA1  
External resistor from this node to  
defines the full scale output  
VSS25AA1  
current for the DACs.  
AB  
AP  
poa_abb_50option External reference voltage output.  
VBIAS  
Analog Power (2 pads for this node is  
vdd2t_abb  
VDD25AA1  
recommended.)  
Analog Ground (2 pads for this node is  
AG  
DP  
vss2t_abb  
VSS25AA1  
VDD25AD1  
recommended)  
vdd2t_abb  
Digital Power  
DG  
AG  
AO  
vss2t_abb  
vbb_abb  
Digital Ground  
VSS25AD1  
VABB  
Substrate Bias(the same with ground level)  
poa_abb_50option Analog Current Output  
IO1  
SEC ASIC  
ANALOG  
2 / 10  

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