512 Mb (64 MB), 3.0 V Serial NOR Flash Memory
Wide temperature range
Table of contents
Table of contents
General description ...........................................................................................................................1
Features ...........................................................................................................................................1
Performance summary ......................................................................................................................3
Table of contents...............................................................................................................................4
1 Product overview ...........................................................................................................................9
1.1 Key feature ..............................................................................................................................................................9
2 Connection diagrams ....................................................................................................................10
2.1 36-lead ceramic flatpack (36 FP)..........................................................................................................................10
3 Signal descriptions .......................................................................................................................11
3.1 Input/output summary.........................................................................................................................................11
3.2 Multiple Input / Output (MIO)...............................................................................................................................12
3.3 Serial Clock (SCK1, SCK2) .....................................................................................................................................12
3.4 Chip Select (CS1#, CS2#).......................................................................................................................................12
3.5 Input Output IO0–IO7 ...........................................................................................................................................12
3.6 RESET1#, RESET2#................................................................................................................................................12
3.7 Voltage Supply (VDD)............................................................................................................................................12
3.8 Supply and Signal Ground (VSS) ..........................................................................................................................12
3.9 Not Connected (NC) ..............................................................................................................................................13
3.10 Reserved for Future Use (RFU) ...........................................................................................................................13
3.11 Do Not Use (DNU)................................................................................................................................................13
4 Block diagrams.............................................................................................................................14
4.1 Logic block diagram..............................................................................................................................................14
4.2 System block diagram ..........................................................................................................................................14
5 Signal protocols............................................................................................................................15
5.1 SPI clock modes ....................................................................................................................................................15
5.1.1 Single data rate (SDR)........................................................................................................................................15
5.1.2 Double data rate (DDR)......................................................................................................................................16
5.2 Command protocol...............................................................................................................................................16
5.2.1 Command sequence examples .........................................................................................................................18
5.3 Interface states .....................................................................................................................................................21
5.3.1 Power-off............................................................................................................................................................22
5.3.2 Low power hardware data protection ..............................................................................................................22
5.3.3 Hardware (Warm) reset .....................................................................................................................................22
5.3.4 Interface standby...............................................................................................................................................22
5.3.5 Instruction cycle (Legacy SPI mode).................................................................................................................22
5.3.6 Instruction cycle (QPI mode).............................................................................................................................22
5.3.7 Single input cycle — Host to Memory transfer .................................................................................................22
5.3.8 Single latency (Dummy) cycle ...........................................................................................................................23
5.3.9 SPI Single output cycle - Memory to Host transfer...........................................................................................23
5.3.10 QPP or QOR address input cycle .....................................................................................................................23
5.3.11 Quad input cycle — Host to Memory transfer.................................................................................................23
5.3.12 Quad latency (Dummy) cycle ..........................................................................................................................23
5.3.13 Quad output cycle — Memory to Host transfer ..............................................................................................23
5.3.14 DDR Quad input cycle — Host to Memory transfer.........................................................................................24
5.3.15 DDR latency cycle.............................................................................................................................................24
5.3.16 DDR quad output cycle — Memory to Host transfer.......................................................................................24
5.4 Data protection.....................................................................................................................................................24
5.4.1 Power-up............................................................................................................................................................24
5.4.2 Low power..........................................................................................................................................................24
5.4.3 Clock pulse count...............................................................................................................................................24
5.4.4 Deep power down (DPD) ...................................................................................................................................24
Datasheet
4 of 152
002-34691 Rev. **
2022-05-25
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