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CYII5FM1300AB-QDC

更新时间： 2024-02-08 12:11:21
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 传感器换能器图像传感器时钟
页数 文件大小 规格书
41页 1703K
描述
1.3 MP CMOS Image Sensor

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CYII5FM1300AB-QDC 技术参数

是否Rohs认证： 符合生命周期：Transferred
Reach Compliance Code：compliant风险等级：5.18
其他特性：ELECTRONIC SNAPSHOT SHUTTER, ROLLING SHUTTER阵列类型：FULL FRAME
主体宽度：9.29 mm主体高度：0.83 mm
主体长度或直径：10.15 mm数据速率：40 Mbps
动态范围：64 dB帧速率：27 fps
水平像素：1280外壳：CERAMIC
主时钟：40 MHz安装特点：SURFACE MOUNT
最大工作电流：60 mA最高工作温度：65 °C
最低工作温度：-30 °C光学格式：2/3 inch
输出接口类型：I2C INTERFACE输出范围：0.50-2.02V
输出类型：DIGITAL VOLTAGE封装形状/形式：RECTANGULAR
像素大小：6.7X6.7 µm电源：3.3 V
灵敏度（V / lx.s）：8.4 V/lx.s传感器/换能器类型：IMAGE SENSOR,CMOS
子类别：CCD Image Sensors最大供电电压：4.5 V
最小供电电压：3 V表面贴装：YES
端接类型：SOLDER垂直像素：1024
Base Number Matches：1

CYII5FM1300AB-QDC 数据手册

 浏览型号CYII5FM1300AB-QDC的Datasheet PDF文件第4页浏览型号CYII5FM1300AB-QDC的Datasheet PDF文件第5页浏览型号CYII5FM1300AB-QDC的Datasheet PDF文件第6页浏览型号CYII5FM1300AB-QDC的Datasheet PDF文件第8页浏览型号CYII5FM1300AB-QDC的Datasheet PDF文件第9页浏览型号CYII5FM1300AB-QDC的Datasheet PDF文件第10页 
IBIS5-B-1300 CYII5FM1300AB  
Because every register addresses two columns at a time, the  
addressable pixels range in sub-sample mode is from zero to half  
the maximum number of pixels in a row (only even values). For  
instance: 0, 2, 4, 6, 8… 638.  
X-Addressing  
Because of the high pixel rate, the X-shift register selects two  
columns at a time for readout, so it runs at half the system clock  
speed. All even columns are connected to bus A; all odd columns  
to bus B. In the output amplifier, bus A and bus B are combined  
into one stream of pixel data at system clock speed.  
Table 6. X–Sub-sample Patterns  
X_SUB  
X_SWAP12 X_SWAP30 Sub-Sample Pattern  
At the end of the row blanking time, the X_SYNC switch is closed  
while all other switches are open and the decoder output is fed  
to the register. The decoder loads a logical one in one of the  
registers and a logical zero in the rest. This defines the starting  
point of the window in the X direction. As soon as the X_SYNC  
signal is released, the register starts shifting from the start  
position.  
0
1
1
1
1
0
0
1
0
1
0
0
0
1
1
XXXXXXXX  
XXOOXXOO  
XOXOXOXO  
OXOXOXOX  
OOXXOOXX  
When no sub-sampling is required, X_SUB is inactive. The  
pointer in the shift-register moves one bit at a time.  
Y-addressing  
When sub-sampling is enabled, X_SUB is activated. The shift  
register moves two bits at a time. Taking into account that every  
register selects two columns, hence two pixels sub-sampling  
results in the pattern ’XXOOXXOO’ when eight pixels are  
considered. Suppose the columns are numbered from left to right  
starting with 0 (zero) and sub-sampling is enabled:  
For symmetry reasons, the sub-sampling modes in the  
Y-direction are the same as in X-direction.  
Table 7. Y–Sub-Sample Patterns  
Y_SUB  
Y_SWAP12 Y_SWAP30 Sub-Sample Pattern  
If columns 1 and 2, 5 and 6, 9 and 10 … are swapped using the  
0
1
1
1
1
0
0
1
0
1
0
0
0
1
1
XXXXXXXX  
XXOOXXOO  
XOXOXOXO  
OXOXOXOX  
OOXXOOXX  
SWAP_12 switches,  
a normal sub-sampling pattern of  
’XOXOXOXO’ is obtained.  
If columns 3 and 4, 7 and 8, 11 and 12 … are swapped using the  
SWAP_30 switches, the pattern is ’OXOXOXOX’.  
If both the SWAP_12 and SWAP_30 switches are closed, pattern  
’OOXXOOXX’ is obtained.  
Figure 6. Column Structure  
COL(i)  
COL(i+2)  
COL(i+1)  
COL(i+3)  
X_SWAP30  
X_SWAP12  
Column  
A
B
A
B
A
B
amplifiers  
BUS_A  
BUS_B  
Output  
Reg(n)  
Reg(n+1)  
Reg(n+2)  
amplifier  
SYS_CLOCK 1/2  
X_SUB  
X_SYNC  
DEC(n+1)  
DEC(n+2)  
Document #: 38-05710 Rev. *E  
Page 7 of 41  
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