Datasheet > CY8CLED04G01

CY8CLED04G01

更新时间： 2024-01-13 06:48:20

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		驱动器
页数	文件大小	规格书
52页	1388K
描述
PowerPSoC Intelligent LED Driver

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数据手册

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CY8CLED04G01 数据手册

CY8CLED04D01, CY8CLED04D02

CY8CLED04G01, CY8CLED03D01

CY8CLED03D02, CY8CLED03G01

CY8CLED02D01, CY8CLED01D01

15.20 PSoC Core I C Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and T ≤ 115°C. Typical parameters apply to 5V at 25°C. These are for design guidance only.

Table 15-35. AC Characteristics of the I²C SDA and SCL Pins

Standard Mode

Fast Mode

Symbol

Description

SCL Clock Frequency

Units

Notes

Min

Max

100

–

Min

Max

f_SCLI2C

400

–

kHz

t_HDSTAI2CHold Time (repeated) START Condition. After

this period, the first clock pulse is generated.

4.0

0.6

μs

t_LOWI2C

t_HIGHI2C

LOW Period of the SCL Clock

HIGH Period of the SCL Clock

4.7

4.0

4.7

–

1.3

0.6

–

μs

t_SUSTAI2CSetup Time for a Repeated START Condition

t_HDDATI2CData Hold Time

0.6

t_SUDATI2CData Setup Time

250

4.0

4.7

100^[10]

t_SUSTOI2CSetup Time for STOP Condition

0.6

t_BUFI2C

Bus Free Time Between a STOP and START

Condition

1.3

t_SPI2C

Pulse Width of Spikes are Suppressed by the

Input Filter.

–

Figure 15-8. Definition of Timing for Fast/Standard Mode on the I²C Bus

Note

10. A fast mode I2C bus device can be used in a standard mode I2C bus system, but the requirement t

≥ 250 ns must then be met. This is automatically the case

SUDATI2

if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the

SDA line trmax + t

= 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification) before the SCL line is released.

SUDATI2

Document Number: 001-46319 Rev. *G

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