Datasheet > CY7C4122KV13-933FCXI

CY7C4122KV13-933FCXI

更新时间： 2024-01-02 22:15:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
46页	1157K
描述
144-Mbit QDRâ¢-IV XP SRAM

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中文翻译

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数据手册

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CY7C4122KV13/CY7C4142KV13

144-Mbit QDR™-IV XP SRAM

Features

Configurations

CY7C4122KV13 – 8M × 18

CY7C4142KV13 – 4M × 36

■ 144-Mbit density (8M × 18, 4M × 36)

■ Total Random Transaction Rate^[1]of 2132 MT/s

Functional Description

■ Maximum operating frequency of 1066 MHz

■ Read latency of 8.0 clock cycles and write latency of 5.0 clock

cycles

The QDR™-IV XP (Xtreme Performance) SRAM is

high-performance memory device optimized to maximize the

number of random transactions per second by the use of two

independent bidirectional data ports.

■ Eight-bank architecture enables one access per bank per cycle

■ Two-word burst on all accesses

These ports are equipped with DDR interfaces and designated

as port A and port B respectively. Accesses to these two data

ports are concurrent and independent of each other. Access to

each port is through a common address bus running at DDR. The

control signals are running at SDR and determine if a read or

write should be performed.

■ Dual independent bidirectional data ports

❐ Double data rate (DDR) data ports

❐ Supports concurrent read/write transactions on both ports

■ Single address port used to control both data ports

❐ DDR address signaling

There are three types of differential clocks:

■ Single data rate (SDR) control signaling

■ (CK, CK#) for address and command clocking

■ (DKA, DKA#, DKB, DKB#) for data input clocking

■ (QKA, QKA#, QKB, QKB#) for data output clocking

■ High-speed transceiver logic (HSTL) and stub series termi-

nated logic (SSTL) compatible signaling (JESD8-16A

compliant)

❐ I/O V_DDQ= 1.2 V ± 50 mV or 1.25 V ± 50 mV

Addresses for port A are latched on the rising edge of the input

clock (CK), and addresses for port B are latched on the falling

edge of the input clock (CK).

■ Pseudo open drain (POD) signaling (JESD8-24 compliant)

❐ I/O V_DDQ= 1.1 V ± 50 mV or 1.2 V ± 50 mV

This QDR-IV XP SRAM is internally partitioned into eight internal

banks. Each bank can be accessed once for every clock cycle,

enabling the SRAM to operate at high frequencies.

■ Core voltage

❐ V_DD= 1.3 V ± 40 mV

The QDR-IV XP SRAM device is offered in a two-word burst

option and is available in × 18 and × 36 bus width configurations.

■ On-die termination (ODT)

❐ Programmable for clock, address/command, and data inputs

For an ×18 bus-width configuration, there are 22 address bits,

and for an ×36 bus width configuration, there are 21 address bits

respectively.

■ Internal self-calibration of output impedance through ZQ pin

■ Bus inversion to reduce switching noise and power

❐ Programmable on/off for address and data

An on-chip ECC circuitry detects and corrects all single-bit

memory errors including those induced by soft error events, such

as cosmic rays and alpha particles. The resulting SER of these

■ Address bus parity error protection

■ Training sequence for per-bit deskew

devices is expected to be less than 0.01 FITs/Mb,

four-order-of-magnitude improvement over previous generation

SRAMs.

■ On-chip error correction code (ECC) to reduce soft error rate

(SER)

For a complete list of related resources, click here.

■ JTAG 1149.1 test access port (JESD8-26 compliant)

❐ 1.3-V LVCMOS signaling

■ Available in 361-ball FCBGA Pb-free package (21 × 21 mm)

Selection Guide

QDR-IV

2132 (MT/s)

QDR-IV

1866 (MT/s)

Description

Unit

Maximum operating frequency

Maximum operating current

1066

4100

4500

933

3400

4000

MHz

×18

×36

Note

1. Random Transaction Rate (RTR) is defined as the number of fully random memory accesses (reads or writes) that can be performed on the memory. RTR is measured

in million transactions per second.

Cypress Semiconductor Corporation

Document Number: 001-68255 Rev. *Q

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 21, 2017

12 3 4 5 6 7...46

中文翻译

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与CY7C4122KV13-933FCXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C412-40LMB	CYPRESS	获取价格	FIFO, 512X9, 40ns, Asynchronous, CMOS, CQCC32,
CY7C412-40PC	CYPRESS	获取价格	FIFO, 512X9, 40ns, Asynchronous, CMOS, PDIP28,
CY7C412-65JC	CYPRESS	获取价格	FIFO, 512X9, 65ns, Asynchronous, CMOS, PQCC32,
CY7C412-65PC	CYPRESS	获取价格	FIFO, 512X9, 65ns, Asynchronous, CMOS, PDIP28,
CY7C4141KV13	CYPRESS	获取价格	144-Mbit QDRâ¢-IV HP SRAM
CY7C4141KV13-600FCXC	CYPRESS	获取价格	144-Mbit QDRâ¢-IV HP SRAM
CY7C4141KV13-633FCXI	CYPRESS	获取价格	QDR SRAM, 4MX36, CMOS, PBGA361, 21 X 21 MM, 2.515 MM HEIGHT, LEAD FREE, FCBGA-361
CY7C4141KV13-633FCXI	INFINEON	获取价格	Synchronous SRAM
CY7C4141KV13-667FCXC	CYPRESS	获取价格	QDR SRAM, 4MX36, CMOS, PBGA361, 21 X 21 MM, 2.515 MM HEIGHT, LEAD FREE, FCBGA-361
CY7C4141KV13-667FCXC	INFINEON	获取价格	Synchronous SRAM

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