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CY7C2563XV18-633BZXC PDF预览

CY7C2563XV18-633BZXC

更新时间： 2024-01-28 23:40:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
29页 614K
描述
72-Mbit QDR® II Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

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CY7C2563XV18-633BZXC 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：BGA包装说明：LBGA, BGA165,11X15,40
针数：165Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
Factory Lead Time：1 week风险等级：1.95
最长访问时间：0.45 ns其他特性：PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：633 MHzI/O 类型：SEPARATE
JESD-30 代码：R-PBGA-B165JESD-609代码：e1
长度：15 mm内存密度：75497472 bit
内存集成电路类型：QDR SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：165字数：4194304 words
字数代码：4000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：4MX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装等效代码：BGA165,11X15,40封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：1.5,1.8 V
认证状态：Not Qualified座面最大高度：1.4 mm
最大待机电流：1.165 A最小待机电流：1.7 V
子类别：SRAMs最大压摆率：1.165 mA
最大供电电压 (Vsup)：1.9 V最小供电电压 (Vsup)：1.7 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：13 mm
Base Number Matches：1

CY7C2563XV18-633BZXC 数据手册

 浏览型号CY7C2563XV18-633BZXC的Datasheet PDF文件第2页浏览型号CY7C2563XV18-633BZXC的Datasheet PDF文件第3页浏览型号CY7C2563XV18-633BZXC的Datasheet PDF文件第4页浏览型号CY7C2563XV18-633BZXC的Datasheet PDF文件第5页浏览型号CY7C2563XV18-633BZXC的Datasheet PDF文件第6页浏览型号CY7C2563XV18-633BZXC的Datasheet PDF文件第7页 
CY7C2563XV18, CY7C2565XV18  
72-Mbit QDR® II+ Xtreme SRAM Four-Word  
Burst Architecture (2.5 Cycle Read Latency) with ODT  
72-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT  
Features  
Configurations  
■ Separate independent read and write data ports  
❐ Supports concurrent transactions  
With Read Cycle Latency of 2.5 cycles  
CY7C2563XV18 – 4 M × 18  
■ 633 MHz clock for high bandwidth  
CY7C2565XV18 – 2 M × 36  
■ Four-word burst for reducing address bus frequency  
Functional Description  
■ Double data rate (DDR) interfaces on both read and write ports  
The CY7C2563XV18 and CY7C2565XV18 are 1.8 V  
Synchronous Pipelined SRAMs, equipped with QDR II+  
architecture. Similar to QDR II architecture, QDR II+ architecture  
consists of two separate ports: the read port and the write port to  
access the memory array. The read port has dedicated data  
outputs to support read operations and the write port has  
dedicated data inputs to support write operations. QDR II+  
architecture has separate data inputs and data outputs to  
completely eliminate the need to “turn-around” the data bus that  
exists with common I/O devices. Each port is accessed through  
a common address bus. Addresses for read and write addresses  
are latched on alternate rising edges of the input (K) clock.  
Accesses to the QDR II+ Xtreme read and write ports are  
completely independent of one another. To maximize data  
throughput, both read and write ports are equipped with DDR  
interfaces. Each address location is associated with four 18-bit  
words (CY7C2563XV18), or 36-bit words (CY7C2565XV18) that  
burst sequentially into or out of the device. Because data is  
transferred into and out of the device on every rising edge of both  
input clocks (K and K), memory bandwidth is maximized while  
simplifying system design by eliminating bus “turn-arounds”.  
(data transferred at 1266 MHz) at 633 MHz  
■ Available in 2.5 clock cycle latency  
■ Two input clocks (K and K) for precise DDR timing  
❐ SRAM uses rising edges only  
■ Echo clocks (CQ and CQ) simplify data capture in high-speed  
systems  
■ Data valid pin (QVLD) to indicate valid data on the output  
■ On-die termination (ODT) feature  
❐ Supported for D[x:0], BWS[x:0], and K/K inputs  
■ Single multiplexed address input bus latches address inputs  
for read and write ports  
■ Separate port selects for depth expansion  
■ Synchronous internally self-timed writes  
■ QDR® II+ Xtreme operates with 2.5 cycle read latency when  
DOFF is asserted HIGH  
■ OperatessimilartoQDRIdevicewith1cyclereadlatencywhen  
DOFF is asserted LOW  
These devices have an on-die termination feature supported for  
D[x:0], BWS[x:0], and K/K inputs, which helps eliminate external  
termination resistors, reduce cost, reduce board area, and  
simplify board routing.  
■ Available in × 18, and × 36 configurations  
■ Full data coherency, providing most current data  
Depth expansion is accomplished with port selects, which  
enables each port to operate independently.  
■ Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to 1.6 V  
❐ Supports 1.5 V I/O supply  
All synchronous inputs pass through input registers controlled by  
the K or K input clocks. All data outputs pass through output  
registers controlled by the K or K input clocks. Writes are  
conducted with on-chip synchronous self-timed write circuitry.  
■ HSTL inputs and variable drive HSTL output buffers  
■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)  
■ Offered in both Pb-free and non Pb-free packages  
■ JTAG 1149.1 compatible test access port  
■ Phase-locked loop (PLL) for accurate data placement  
Selection Guide  
Description  
Maximum Operating Frequency  
633 MHz  
633  
600 MHz Unit  
600  
1100  
1570  
MHz  
mA  
Maximum Operating Current  
× 18  
× 36  
1165  
1660  
Cypress Semiconductor Corporation  
Document Number: 001-68997 Rev. *B  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised June 20, 2012  
1234567...29

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CY7C2563XV18-633BZXC 替代型号

型号 品牌 替代类型 描述 数据表
CY7C2563XV18-633BZC CYPRESS

完全替代

 72-Mbit QDR® II Xtreme SRAM Four-Word Burst

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