CY7C1041B
256K x 16 Static RAM
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A17). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A17).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Features
• High speed
— tAA = 12 ns
• Low active power
— 1540 mW (max.)
• Low CMOS standby power (L version)
— 2.75 mW (max.)
• 2.0V Data Retention (400 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
Functional Description
The CY7C1041B is a high-performance CMOS static RAM
The CY7C1041B is available in
a
standard 44-pin
organized as 262,144 words by 16 bits.
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
Logic Block Diagram
Pin Configuration
SOJ
INPUT BUFFER
TSOP II
Top View
A
44
1
0
A
A
17
0
A
43
42
41
40
39
38
37
36
35
34
33
1
A
A
16
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
A
2
A
A
15
2
I/O0–I/O7
I/O8–I/O15
256K x 16
ARRAY
1024 x 4096
A
3
A
OE
3
A
4
BHE
BLE
A
4
A
5
CE
A
6
I/O
I/O
0
15
A
7
I/O
I/O
I/O
1
14
13
12
A
8
I/O
2
I/O
V
I/O
3
V
SS
CC
COLUMN
V
V
SS
CC
DECODER
32
I/O
I/O
I/O
4
5
6
7
11
10
9
8
31
30
29
28
27
26
25
I/O
I/O
I/O
I/O
I/O
WE 17
NC
BHE
18
A
A
14
5
WE
CE
OE
19
A
A
6
13
A
20
21
22
A
12
11
7
BLE
A
A
24
23
8
A
A
10
9
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05142 Rev. *A
Revised March 24, 2005