Datasheet > CY39015V144-83BBI

CY39015V144-83BBI

更新时间： 2024-01-08 14:26:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		输入元件可编程逻辑
页数	文件大小	规格书
57页	1166K
描述
Loadable PLD, 15ns, CMOS, PBGA144, 1 MM PITCH, FBGA-144

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CY39015V144-83BBI 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	BGA,
针数：	144	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.92
其他特性：	CAN ALSO OPERATE WITH 3.3V SUPPLY	JESD-30 代码：	S-PBGA-B144
专用输入次数：		I/O 线路数量：	92
端子数量：	144	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	0 DEDICATED INPUTS, 92 I/O
输出函数：	MACROCELL	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装形状：	SQUARE
封装形式：	GRID ARRAY	峰值回流温度（摄氏度）：	NOT SPECIFIED
可编程逻辑类型：	LOADABLE PLD	传播延迟：	15 ns
认证状态：	Not Qualified	最大供电电压：	2.7 V
最小供电电压：	2.3 V	标称供电电压：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	BALL
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
Base Number Matches：	1

CY39015V144-83BBI 数据手册

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Delta39K™ ISR™

CPLD Family

PRELIMINARY

CPLDs at FPGA Densities™

•Multiple I/O standards supported

Features

—LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI, SSTL2

•High density

(I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+

— 15K to 350K usable gates

— 256 to 5376 macrocells

— 92 to 520 maximum I/O pins

•Compatible with NOBL™, ZBT™, and QDR™ SRAMs

•Programmable slew rate control on each I/O pin

•User-Programmable Bus Hold capability on each I/O pin

•Fully PCI compliant (to 66 MHz 64-bit PCI spec rev2.2)

•Compact PCI hot swap compatible

•Multiple package/pinout offering across all densities

—144 to 676 pins in PQFP, BGA and FBGA packages

—Same pinout for 3.3V/2.5V and 1.8V devices

—Simplifies design migration across density

—Self-Boot™ solution in BGA and FBGA packages

•In-System Reprogrammable™ (ISR™)

— 12 Dedicated Inputs including 4 clock pins, 4 global

control signal pins and 4 JTAG interface pins for

reconfigurability

•Embedded Memory

— 40K to 840K bits embedded SRAM

• 32K to 672K bits of (single port) Cluster memory

• 8K to 168K bits of (dual port) Channel memory

•High speed - 250-MHz in-system operation

•AnyVolt™ interface

—JTAG-compliant on-board programming

— 3.3V, 2.5V and 1.8V V_CCversions available

—Design changes don’t cause pinout changes

•IEEE1149.1 JTAG boundary scan

— 3.3V, 2.5V and 1.8V I/O capability on all versions

• Low Power Operation

— 0.18-µm 6-layer metal SRAM-based logic process

— Full-CMOS implementation of product term array

Development Software

— Standby current as low as 100 µA at 1.8V V_CC

•Simple timing model

•Warp™

—IEEE 1076/1164 VHDL or IEEE 1364 Verilog context

sensitive editing.

— Nopenaltyfor usingfull16product terms /macrocell

— No delay for single product term steering or sharing

•Flexible clocking

—Active-HDL FSM graphical finite state machine editor

—Active-HDL SIM post-synthesis timing simulator

—Architecture Explorer for detailed design analysis

—Static Timing Analyzer for critical path analysis

—Available on Windows 95, 98 & NT for $99

— 4 synchronous clocks per device

— 1 spread-aware PLL drives all 4 clock networks

— Locally generated Product Term clock

— Clock polarity control at each register

—Supports all Cypress Programmable Logic Products

•Carry-chain logic for fast and efficient arithmetic opera-

tions

Delta39K™ ISR CPLD Family Members

[2]

Standby I_CC

Cluster Channel

memory memory Maximum

f_MAX2Speed-t_PD

Pin-to-Pin

T_A=25°C

Typical

Gates^[1]

Device

39K15

Macrocells

256

(Kbits)

I/O Pins

(MHz)

256

238

222

181

167

154

(ns)

6.5

7.0

7.5

8.5

9.0

3.3/2.5V

1.8V

8K–24K

16K–48K

134

10 mA

100 µA

200 µA

300 µA

600 µA

1250 µA

1500 µA

2100 µA

39K30

512

176

39K50

23K–72K

768

218

39K100

39K165

39K200

39K250

39K350

46K–144K

77K–241K

92K–288K

115K–361K

161K–505K

1536

2560

3072

3840

5376

192

320

384

480

672

302

386

428

120

168

470

520

Note:

1. Upper limit of typical gates is calculated by assuming only 10% of the channel memory is used.

2. Standby I_CCvalues are with PLL not utilized, no output load and stable inputs

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-03039 Rev. **

Revised April 4, 2001

12 3 4 5 6 7...57

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与CY39015V144-83BBI相关器件

型号	品牌	获取价格	描述	数据表
CY39015V208-125NTC	CYPRESS	获取价格	Loadable PLD, 10ns, CMOS, PQFP208, THERMALLY ENHANCED, QFP-208
CY39015V208-250NTC	CYPRESS	获取价格	Loadable PLD, 6.5ns, CMOS, PQFP208, THERMALLY ENHANCED, QFP-208
CY39015V256-125BBC	CYPRESS	获取价格	Loadable PLD, 10ns, CMOS, PBGA256, 17 X 17 MM, 1.60 MM HEIGHT, 1 MM PITCH, TFBGA-256
CY39015V256-125MBI	CYPRESS	获取价格	Loadable PLD, 10ns, CMOS, PBGA256, 17 X 17 MM, 1.60 MM HEIGHT, 1 MM PITCH, TFBGA-256
CY39015V256-250BBC	CYPRESS	获取价格	Loadable PLD, 6.5ns, CMOS, PBGA256, 17 X 17 MM, 1.60 MM HEIGHT, 1 MM PITCH, TFBGA-256
CY39015V256-250MBC	CYPRESS	获取价格	Loadable PLD, 6.5ns, CMOS, PBGA256, 17 X 17 MM, 1.60 MM HEIGHT, 1 MM PITCH, TFBGA-256
CY39015V256-83BBI	CYPRESS	获取价格	Loadable PLD, 15ns, CMOS, PBGA256, 17 X 17 MM, 1.60 MM HEIGHT, 1 MM PITCH, TFBGA-256
CY39015Z144-125BBC	CYPRESS	获取价格	Loadable PLD, 10ns, CMOS, PBGA144, 1 MM PITCH, FBGA-144
CY39015Z144-125BBI	CYPRESS	获取价格	Loadable PLD, 10ns, CMOS, PBGA144, 1 MM PITCH, FBGA-144
CY39015Z144-83BBC	CYPRESS	获取价格	Loadable PLD, 15ns, CMOS, PBGA144, 1 MM PITCH, FBGA-144

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