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CY25812SXI

更新时间： 2024-02-23 08:56:25
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 晶体时钟发生器微控制器和处理器外围集成电路光电二极管
页数 文件大小 规格书
11页 307K
描述
Spread Spectrum Clock Generator

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CY25812SXI 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：TSSOP, TSSOP8,.25针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.31.00.01风险等级：5.77
Is Samacsys：NJESD-30 代码：R-PDSO-G8
JESD-609代码：e3长度：4.4 mm
湿度敏感等级：3端子数量：8
最高工作温度：70 °C最低工作温度：
最大输出时钟频率：64 MHz封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP8,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：3.3 V
主时钟/晶体标称频率：32 MHz认证状态：Not Qualified
座面最大高度：1.1 mm子类别：Clock Generators
最大压摆率：35 mA最大供电电压：3.63 V
最小供电电压：2.97 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：20
宽度：3 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHER
Base Number Matches：1

CY25812SXI 数据手册

 浏览型号CY25812SXI的Datasheet PDF文件第1页浏览型号CY25812SXI的Datasheet PDF文件第2页浏览型号CY25812SXI的Datasheet PDF文件第4页浏览型号CY25812SXI的Datasheet PDF文件第5页浏览型号CY25812SXI的Datasheet PDF文件第6页浏览型号CY25812SXI的Datasheet PDF文件第7页 
CY25811/12/14  
Table 2. Spread% Selection (continued)  
XIN  
S1 = 0  
S1 = 0  
S1 = 0  
S0 = 1  
S1 = M  
S0 = 0  
S1 = 1  
S0 = 1  
S1 = 1  
S0 = 0  
S1 = M  
S0 = 1  
S1 = 1  
S0 = M  
S1 = M  
S0 = M  
(MHz)  
FRSEL  
S0 = 0  
S0 = M  
20-24  
24-28  
28-32  
M
M
M
±1.3  
±1.2  
±1.1  
±1.1  
± 0.9  
± 0.9  
± 0.5  
± 0.5  
± 0.4  
± 0.4  
± 0.4  
± 0.3  
–2.7  
–2.5  
–2.3  
–1.9  
–1.8  
–1.7  
–1.7  
–1.5  
–1.4  
–0.6  
–0.6  
–0.5  
0
0
0
3-Level Digital Inputs  
S0, S1, and FRSEL digital inputs are designed to sense 3  
different logic levels designated as High “1”, Low “0” and  
Middle “M”. With this 3-Level digital input logic, the 3-Level  
Logic is able to detect 9 different logic states.  
S0, S1 and FRSEL pins include an on chip 20K (10K/10K)  
resistor divider. No external application resistors are needed  
to implement the 3-Level logic levels as shown below:  
Logic Level “0”: 3–Level logic pin connected to GND.  
Logic Level “M”: 3–Level logic pin left floating (no connection).  
Logic Level “1”: 3–Level logic pin connected to VDD  
.
Figure 1 illustrates how to implement 3–Level Logic.  
LOGIC  
LOGIC  
LOGIC  
MIDDLE (M)  
LOW (0)  
HIGH (H)  
S0, S1  
and  
S0, S1  
and  
S0, S1  
and  
FRSEL  
FRSEL  
to VSS  
FRSEL  
to VDD  
UNCONNECTED  
VSS  
Figure 1. 3–Level Logic  
Modulation Rate  
Table 3. Modulation Rate Divider Ratios  
Input Frequency Range  
Divider Ratio  
(DR)  
Spread Spectrum Clock Generators utilize frequency  
modulation (FM) to distribute energy over a specific band of  
frequencies. The maximum frequency of the clock (fmax) and  
minimum frequency of the clock (fmin) determine this band of  
frequencies. The time required to transition from fmin to fmax  
and back to fmin is the period of the Modulation Rate. The  
Modulation Rate of SSCG clocks are generally referred to in  
terms of frequency, or  
FRSEL  
(MHz)  
4 to 8  
0
128  
256  
512  
1
M
8 to 16  
16 to 32  
Input and Output Frequency Selection  
fmod = 1/Tmod.  
The relationship between input frequency versus output  
frequency in terms of device selection and FRSEL setting is  
given in Table 4. As shown, the input frequency range is  
selected by FRSEL and is the same for CY25811, CY25812,  
and CY25814. The selection of CY25811 (1x), CY25812 (2x)  
or CY25814 (4x) determines the frequency multiplication at  
the output (SSCLK, Pin 5) with respect to input frequency  
(XIN, Pin-1).  
The input clock frequency, fin, and the internal divider  
determine the Modulation Rate.  
In the case of CY25811/2/4 devices, the (Spread Spectrum)  
modulation Rate, fmod, is given by the following formula:  
fmod = fin/DR  
where; fmod is the Modulation Rate, fin is the Input Frequency  
and DR is the Divider Ratio as given in Table 3. Notice that  
Input Frequency Range is set by FRSEL.  
Document #: 38-07112 Rev. *E  
Page 3 of 11  
1234567...11

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