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CY25812SIT

更新时间： 2024-01-21 00:59:00
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟发生器
页数 文件大小 规格书
11页 307K
描述
Spread Spectrum Clock Generator

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CY25812SIT 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：TSSOP, TSSOP8,.25针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.31.00.01风险等级：5.77
Is Samacsys：NJESD-30 代码：R-PDSO-G8
JESD-609代码：e3长度：4.4 mm
湿度敏感等级：3端子数量：8
最高工作温度：70 °C最低工作温度：
最大输出时钟频率：64 MHz封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP8,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：3.3 V
主时钟/晶体标称频率：32 MHz认证状态：Not Qualified
座面最大高度：1.1 mm子类别：Clock Generators
最大压摆率：35 mA最大供电电压：3.63 V
最小供电电压：2.97 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：20
宽度：3 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHER
Base Number Matches：1

CY25812SIT 数据手册

 浏览型号CY25812SIT的Datasheet PDF文件第1页浏览型号CY25812SIT的Datasheet PDF文件第3页浏览型号CY25812SIT的Datasheet PDF文件第4页浏览型号CY25812SIT的Datasheet PDF文件第5页浏览型号CY25812SIT的Datasheet PDF文件第6页浏览型号CY25812SIT的Datasheet PDF文件第7页 
CY25811/12/14  
Pin Definitions  
Pin No.  
Name  
Xin/CLK  
VSS  
S1  
S0  
SSCLK  
FRSEL  
VDD  
Type  
Description  
Crystal, ceramic resonator or clock input pin.  
Power supply ground.  
Digital Spread% control pin. 3-Level input (H-M-L). Default = M.  
Digital Spread% control pin. 3-Level input (H-M-L). Default = M.  
Spread Spectrum output clock.  
Input frequency range selection digital control input. 3-Level input (H-M-L). Default = M.  
Positive power supply.  
1
2
3
4
5
6
7
8
XOUT  
Crystal or ceramic resonator output pin.  
Spread % for each Spread Mode with the option of a  
Non-Spread mode for system test and verification purposes.  
Functional Description  
The CY25811/12/14 products are Spread Spectrum Clock  
Generator (SSCG) ICs used for the purpose of reducing  
electromagnetic interference (EMI) found in today’s  
high-speed digital electronic systems.  
The devices use a Cypress proprietary phase-locked loop  
(PLL) and Spread Spectrum Clock (SSC) technology to  
synthesize and modulate the frequency of the input clock. By  
frequency modulating the clock, the measured EMI at the  
fundamental and harmonic frequencies is greatly reduced.  
The CY25811/12/14 products are available in an 8-pin SOIC  
(150-mil.) package with a Commercial operating temperature  
range of 0 to 70°C and Industrial Temperature range of –40 to  
85°C. Refer to CY25568 for multiple clock output options such  
as modulated and unmodulated clock outputs or Power-down  
function.  
For  
Automotive  
applications,  
refer  
to  
CY25811/12/14SE data sheet.  
Input Frequency Range and Selection  
This reduction in radiated energy can significantly reduce the  
cost of complying with regulatory agency requirements and  
improve time to market without degrading system perfor-  
mance.  
The input frequency range is 4 to 32 MHz and accepts clock,  
crystal and ceramic resonator inputs. The output clock can be  
selected to produce 1x, 2x, or 4x multiplication of the input  
frequency with Spread Spectrum Frequency Modulation.  
The use of 2x or 4x frequency multiplication eliminates the  
need for higher order crystals and enables the user to  
generate up to 128-MHz Spread Spectrum Clock (SSC) by  
using only first order crystals. This will reduce the cost while  
improving the system clock accuracy, performance and  
complexity.  
The CY25811/12/14 input frequency range is 4 to 32 MHz.  
This range is divided into three segments and controlled by  
3-Level FRSEL pin as given in Table 1.  
Table 1. Input Frequency Selection  
FRSEL  
Input Frequency Range  
4.0 to 8.0 MHz  
0
1
8.0 to 16.0 MHz  
M
16.0 to 32.0 MHz  
Spread% Selection  
The CY25811/12/14 SSCG products provide Center-Spread,  
Down-Spread and No-Spread functions. The amount of  
Spread% is selected by using 3-Level S0 and S1 digital inputs  
and Spread% values are given in Table 2.  
Center Spread or Down Spread frequency modulation can be  
selected by the user based on four discrete values of  
Table 2. Spread% Selection  
XIN  
S1 = 0  
S1 = 0  
S0 = M  
S1 = 0  
S0 = 1  
S1 = M  
S0 = 0  
S1 = 1  
S0 = 1  
S1 = 1  
S0 = 0  
S1 = M  
S0 = 1  
S1 = 1  
S0 = M  
S1 = M  
S0 = M  
(MHz)  
FRSEL  
S0 = 0  
Center  
(%)  
Center  
Center  
Center  
Down  
Down  
Down  
Down  
(%)  
(%)  
(%)  
(%)  
(%)  
(%)  
(%)  
No Spread  
4-5  
5-6  
6-7  
0
0
0
0
1
1
1
1
M
±1.4  
±1.3  
±1.2  
±1.1  
±1.4  
±1.3  
±1.2  
±1.1  
±1.4  
± 1.2  
± 1.1  
± 0.9  
± 0.9  
±1.2  
±1.1  
± 0.9  
± 0.9  
±1.2  
± 0.6  
± 0.5  
± 0.5  
± 0.4  
± 0.6  
± 0.5  
± 0.5  
± 0.4  
± 0.6  
± 0.5  
± 0.4  
± 0.4  
± 0.3  
± 0.5  
± 0.4  
± 0.4  
± 0.3  
± 0.5  
–3.0  
–2.7  
–2.5  
–2.3  
–3.0  
–2.7  
–2.5  
–2.3  
–3.0  
–2.2  
–1.9  
–1.8  
–1.7  
–2.2  
–1.9  
–1.8  
–1.7  
–2.2  
–1.9  
–1.7  
–1.5  
–1.4  
–1.9  
–1.7  
–1.5  
–1.4  
–1.9  
–0.7  
–0.6  
–0.6  
–0.5  
–0.7  
–0.6  
–0.6  
–0.5  
–0.7  
0
0
0
0
0
0
0
0
0
7-8  
8-10  
10-12  
12-14  
14-16  
16-20  
Document #: 38-07112 Rev. *E  
Page 2 of 11  
1234567...11

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