CY25811/12/14
AC Electrical Specifications (Commercial Grade)
Parameter
FIN
TR1
TF1
TR2
TF2
TDCIN
TDCOUT
TCCJ1
TCCJ2
TCCJ3
TCCJ4
TCCJ5
TCCJ6
TSU
Description
Input Frequency Range
Clock Rise Time
Clock Fall Time
Clock Rise Time
Condition
Min.
4
Max.
32
Unit
MHz
ns
ns
ns
ns
%
%
ps
ps
ps
ps
ps
ps
ms
Clock, Crystal or Ceramic Resonator Input
SSCLK, CY25811 and CY25812
SSCLK, CY25811 and CY25812
SSCLK, only CY25814 when FRSEL = M
SSCLK, only CY25814 when FRSEL = M
XIN
2.0
2.0
1.0
1.0
40
40
–
–
–
–
–
5.0
4.4
2.2
2.2
60
Clock Fall Time
Input Clock Duty Cycle
Output Clock Duty Cycle
Cycle-to-Cycle Jitter, Spread on
Cycle-to-Cycle Jitter, Spread on
Cycle-to-Cycle Jitter, Spread on
Cycle-to-Cycle Jitter, Spread on
Cycle-to-Cycle Jitter, Spread on
Cycle-to-Cycle Jitter, Spread on
PLL Lock Time
SSCLK
60
Fin = 4 MHz, Fout = 4 MHz, CY25811
Fin = 8 MHZ, Fout = 8 MHz, CY25811
Fin = 8 MHz, Fout = 16 MHz, CY25812
Fin = 16 MHz, Fout = 32 MHz, CY25812
Fin = 16 MHz, Fout = 64 MHz, CY25814
Fin = 32 MHz, Fout = 128 MHz, CY25814
Fom VDD 3.0V to valid SSCLK
800
450
400
380
380
380
3
–
–
DC Electrical Specifications (Industrial Grade)
Parameter
VDD
VIL
VIM
Description
3.3 Operating Voltage
Input Low Voltage
Input Middle Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
Output High Voltage
Output High Voltage
Input Pin Capacitance
Input Pin Capacitance
Output Load Capacitor
Dynamic Supply Current
Dynamic Supply Current
Dynamic Supply Current
Condition
Min.
3.135
0
0.40VDD 0.60VDD
0.85VDD
Max.
3.465
0.13VDD
Unit
V
V
V
V
V
V
V
V
pF
pF
pF
mA
mA
mA
3.3 ± 5%
S0, S1 and FRSEL Inputs
S0, S1 and FRSEL Inputs
S0, S1 and FRSEL Inputs
IOL = 4 ma, SSCLK Output
IOL = 10 ma, SSCLK Output
IOH = 4 ma, SSCLK Output
IOH = 6 ma, SSCLK Output
XIN (Pin 1) and XOUT (Pin 8)
All Digital Inputs
VIH
VDD
0.4
1.2
–
VOL1
VOL2
VOH1
VOH2
CIN1
CIN2
CL
IDD1
IDD2
IDD3
–
–
2.4
2.0
6.0
3.5
–
–
–
–
–
9.0
6.0
15
26
32
37
SSCLK Output
Fin = 12 MHz, no load
Fin = 24 MHz, no load
Fin = 32 MHz, no load
AC Electrical Specifications (Industrial Grade)
Parameter
FIN
TR1
TF1
TR2
TF2
TDCIN
TDCOUT
TCCJ1
TCCJ2
TCCJ3
TSU
Description
Input Frequency Range
Clock Rise Time
Clock Fall Time
Clock Rise Time
Condition
Clock, Crystal or Ceramic Resonator Input
SSCLK, CY25811 and CY25812
SSCLK, CY25811 and CY25812
SSCLK, only CY25814 when FRSEL = M
SSCLK, only CY25814 when FRSEL = M
XIN
Min.
4
Max.
32
Unit
MHz
ns
ns
ns
ns
%
%
ps
2.0
2.0
1.0
1.0
40
40
–
–
–
–
5.0
4.4
2.2
2.2
60
Clock Fall Time
Input Clock Duty Cycle
Output Clock Duty Cycle
Cycle-to-Cycle Jitter, Spread on
Cycle-to-Cycle Jitter, Spread on
Cycle-to-Cycle Jitter, Spread on
PLL Lock Time
SSCLK
60
Fin = 6MHz, CY25811/12/14
Fin = 12MHZ, CY25811/12/14
Fin = 24MHz, CY25811/12/14
From VDD 3.0V to valid SSCLK
650
400
400
4
ps
ps
ms
Document #: 38-07112 Rev. *E
Page 5 of 11
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