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CS1500-FSZ PDF预览

CS1500-FSZ

更新时间: 2024-02-10 17:19:34
品牌 Logo 应用领域
凌云 - CIRRUS 稳压器开关式稳压器或控制器电源电路开关式控制器功率因数校正光电二极管
页数 文件大小 规格书
22页 828K
描述
Digital Power Factor Correction IC

CS1500-FSZ 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP,
针数:8Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:8.63Is Samacsys:N
模拟集成电路 - 其他类型:POWER FACTOR CONTROLLER控制技术:PULSE WIDTH MODULATION
最大输入电压:15 V最小输入电压:10 V
标称输入电压:13 VJESD-30 代码:R-PDSO-G8
长度:4.9 mm湿度敏感等级:2
功能数量:1端子数量:8
最高工作温度:125 °C最低工作温度:-40 °C
最大输出电流:0.5 A封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE认证状态:Not Qualified
座面最大高度:1.75 mm表面贴装:YES
切换器配置:BOOST最大切换频率:70 kHz
温度等级:AUTOMOTIVE端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:3.9 mmBase Number Matches:1

CS1500-FSZ 数据手册

 浏览型号CS1500-FSZ的Datasheet PDF文件第4页浏览型号CS1500-FSZ的Datasheet PDF文件第5页浏览型号CS1500-FSZ的Datasheet PDF文件第6页浏览型号CS1500-FSZ的Datasheet PDF文件第8页浏览型号CS1500-FSZ的Datasheet PDF文件第9页浏览型号CS1500-FSZ的Datasheet PDF文件第10页 
May ?$shortyear>  
CONFIDENTIAL  
CS1500  
3. INTRODUCTION  
CS1500  
8
NC  
2
5
6
Oscillator  
STBY  
GND  
GD  
3
IAC  
Processor  
Logic  
7
ADC  
VDD  
Protection  
4
FB  
PWM  
Driver  
1
NC  
Figure 9. CS1500 Block Diagram  
The CS1500 digital power factor controller operates in variable  
on-time, variable frequency, discontinuous conduction mode  
(DCM). The CS1500 uses a proprietary digital algorithm to  
maximize the efficiency and reduce the conductive EMI.  
proves system stability and transient response. No  
external feedback error signal compensation components  
are required.  
• Overcurrent Mitigation  
The analog-to-digital converter (ADC) shown in the CS1500  
block diagram in Figure 9 is used to sense the PFC output  
voltage ( Vlink ) and the rectified AC line voltage ( Vrect ) by  
measuring currents through their respective resistors. The  
magnitudes of these currents are measured as a proportion of a  
reference current (IREF) that functions as the reference for the  
ADCs. The digital signal is then processed in a control algorithm  
which determines the behavior of the CS1500 during start-up,  
normal operation, and under fault conditions, such as brownout,  
overvoltage, overcurrent, overpower, and over-temperature  
conditions.  
The CS1500s digital controller algorithm limits the ON  
time of the Power MOSFET by the following equation:  
0.001126  
------------------------  
Ton  
Vrect  
Where Ton is the max time that the power MOSFET is  
turned on and Vrect is the rectified line voltage. In the  
event of a sudden line surge or sporadic, high dv/dt line  
voltages, this equation may not limit the ON time appro-  
priately. For this type of line disturbance, additional pro-  
tection mechanisms such as fusible resistors, fast-blow  
fuses, or other current-limiting devices are recommend-  
ed.  
• DCM with Variable On-Time, Variable Switching Fre-  
quency  
The CS1500 PFC switching frequency varies with the  
Vrect on a cycle-by-cycle basis, and its digital algorithm  
calculates the on-time accordingly for unity power factor.  
Unlike traditional Critical Conduction Mode (CRM) PFC  
controller, CS1500 operates at its low switching frequen-  
cy near the zero-crossing point of the AC input voltage,  
even no switching at all, and it operates at its high switch-  
ing frequency at the peak of its AC input voltage (this is  
the opposite of the switching frequency profile for a CRM  
PFC controller), thus CS1500 reduces switching losses  
especially under light-load conditions, spreads conducted  
EMI energy peaks over a wide frequency band and in-  
creases overall system efficiency.  
• Over Voltage Protection  
Under steady-state conditions, the voltage loop keeps  
PFC output voltage close to its nominal value. Under light  
load startup or feedback loop open conditions, the output  
voltage may pass the overvoltage protection threshold.  
The digital control engine initiates a fast response loop to  
shut down gate driving signal to reduce the energy deliv-  
ered to the output for PFC capacitor protection. When the  
link voltage drop below VOVP-VOVP(Hy), PFC resumes  
normal operation.  
• Optimized Digital Loop Compensation  
The proprietary digital control engine optimizes the feed-  
back error signal using an adaptive control algorithm, im-  
DS849A5  
7

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