CM6535
USB Audio Chip
6.6.4
6.6.5
6.6.6
6.6.7
I2S Mode ..........................................................................................................................27
I2S MCLK/BCLK/LRCK ratio and format for cm6535 ..................................................28
I2S output enable setting and data stream path................................................................29
I2S DSP mode...................................................................................................................30
SPDIF control description........................................................................................................31
SPDIF frame description..................................................................................................31
SPDIF out channel status.................................................................................................32
Digital microphone ..................................................................................................................33
I2C interface .............................................................................................................................34
I2C master mode...............................................................................................................34
I2C-master read with clk_sync mode ..............................................................................35
I2C master device address and control register................................................................35
I2C master memory address pointer (map) register .........................................................35
I2C master memory address pointer (map2) register .......................................................35
I2C master data register....................................................................................................35
I2C Master Control and Status Register 0........................................................................36
I2C master control and status register 1 ...........................................................................36
I2C master download control and status register..............................................................36
6.7
6.7.1
6.7.2
6.8
6.9
6.9.1
6.9.2
6.9.3
6.9.4
6.9.5
6.9.6
6.9.7
6.9.8
6.9.9
6.9.10 I2C master clock period setting register...........................................................................37
6.9.11
I2C slave mode .................................................................................................................38
6.9.12 I2C slave data register ......................................................................................................38
6.9.13 I2C slave status register....................................................................................................38
6.9.14 I2C slave memory address pointer (map) register............................................................39
6.9.15 I2C slave status register....................................................................................................39
SPI interface.............................................................................................................................41
6.10.1 SPI Registers Descriptions...............................................................................................41
6.10.2 SPI Control Register 0 .....................................................................................................41
6.10.3 SPI control register 1 .......................................................................................................42
6.10.4 SPI interrupt.....................................................................................................................42
6.10.5 SPI Control Register 3 .....................................................................................................43
GPIO ........................................................................................................................................44
6.10
6.11
6.11.1
6.11.2
6.11.3
6.11.4
6.11.5
6.11.6
6.11.7
GPO data register.............................................................................................................44
GPI data register ..............................................................................................................44
GPIO direction control register........................................................................................44
GPIO interrupt enable mask register................................................................................44
GPIO debouncing register................................................................................................44
GPI remote choose...........................................................................................................44
GPIO pull-up/down..........................................................................................................45
6.12
Arbitrary sine-tone generator...................................................................................................47
Page 4 / 57
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